Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83441?usp=email )
Change subject: mb/clevo/cml-u/dt: Make use of chipset devicetree ......................................................................
mb/clevo/cml-u/dt: Make use of chipset devicetree
Make use of the alias names defined in the chipset devicetree and remove devices which are equal to the ones from the chipset devicetree.
Change-Id: Ifc882c2ac9d4e9ce2ed4305bdd6859a5d1e1b09c Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/83441 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 15 insertions(+), 53 deletions(-)
Approvals: Michael Niewöhner: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 10db5f8..f078cdf 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -57,8 +57,7 @@ # Actual device tree device domain 0 on subsystemid 0x1558 0x1401 inherit - device pci 00.0 on end # Host Bridge - device pci 02.0 on # Integrated Graphics Device + device ref igpu on register "gfx" = "GMA_DEFAULT_PANEL(0)" register "panel_cfg" = "{ .up_delay_ms = 200, @@ -69,14 +68,11 @@ .backlight_off_delay_ms = 1, }" end - device pci 04.0 on # SA Thermal device + device ref dptf on register "Device4Enable" = "1" end - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI + device ref thermal on end + device ref xhci on # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 @@ -88,15 +84,13 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on # CNVi wifi + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end end - device pci 14.5 off end # SDCard - device pci 15.0 on # I2C #0 + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" @@ -106,16 +100,7 @@ device i2c 15 on end end end - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA + device ref sata on register "SataSalpSupport" = "1" # Port 2 (J_SSD2) register "SataPortsEnable[1]" = "1" @@ -124,24 +109,15 @@ register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on # PCI Express Port 6 + device ref uart2 on end + device ref pcie_rp6 on device pci 00.0 on end # x1 Card reader register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" end - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 + device ref pcie_rp8 on chip drivers/wifi/generic device pci 00.0 on end end @@ -152,7 +128,7 @@ register "PcieRpSlotImplemented[7]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[4]" = "8" @@ -160,10 +136,7 @@ register "PcieRpSlotImplemented[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 + device ref pcie_rp13 on register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[5]" = "12" @@ -171,14 +144,7 @@ register "PcieRpSlotImplemented[12]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip ec/clevo/it5570e device generic 0 on end register "pl2_on_battery" = "15" @@ -187,13 +153,9 @@ device pnp 0c31.0 on end end end - device pci 1f.1 hidden end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA + device ref hda on register "PchHdaAudioLinkHda" = "1" end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device ref smbus on end end end
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Felix Singer (Code Review)