Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81958?usp=email )
Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources ......................................................................
soc/intel/xeon_sp: Add soc_add_dram_resources
SoC specific DRAM resource, e.g. 4GB above memory map, are different across SoC generations. This patch separates the codes so that later SoC integration would be based on this.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 87 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81958/1
diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index b17b773..410578e 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -3,12 +3,14 @@ #include <acpi/acpigen_pci.h> #include <assert.h> #include <console/console.h> +#include <drivers/ocp/include/vpd.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/chip_common.h> +#include <soc/numa.h> #include <soc/soc_util.h> #include <soc/util.h>
@@ -224,3 +226,64 @@ printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", __FILE__, __func__, reg1, reg2); } + +/* + * Add SoC specific DRAM resources + * + * @param dev Pointer of the device to add resource on. + * @param mc_values List of system memory map variables. + * @param start_index The start index for the SoC specific resources. + * + * @return The added resource counts. + */ +int soc_add_dram_resources(struct device *dev, uint64_t mc_values[], int start_index) +{ + const struct resource *res; + int index = start_index; + + if (CONFIG(SOC_INTEL_HAS_CXL)) { + /* 4GiB -> CXL Memory */ + uint32_t gi_mem_size; + gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ + /* + * Memory layout when there is CXL HDM (Host-managed Device Memory): + * -------------- <- TOHM + * CXL memory regions (pds global variable records the base/size of them) + * Processor attached high memory + * -------------- <- 0x100000000 (4GB) + */ + res = upper_ram_end(dev, index++, + mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); + LOG_RESOURCE("high_ram", dev, res); + + /* CXL Memory */ + uint8_t i; + for (i = 0; i < pds.num_pds; i++) { + if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + continue; + + if (CONFIG(OCP_VPD)) { + unsigned long flags = IORESOURCE_CACHEABLE; + int cxl_mode = get_cxl_mode_from_vpd(); + if (cxl_mode == CXL_SPM) + flags |= IORESOURCE_SOFT_RESERVE; + else + flags |= IORESOURCE_STORED; + + res = fixed_mem_range_flags(dev, index++, + (uint64_t)pds.pds[i].base << 26, + (uint64_t)pds.pds[i].size << 26, flags); + if (cxl_mode == CXL_SPM) + LOG_RESOURCE("specific_purpose_memory", dev, res); + else + LOG_RESOURCE("CXL_memory", dev, res); + } + } + } else { + /* 4GiB -> TOHM */ + res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1); + LOG_RESOURCE("high_ram", dev, res); + } + + return index - start_index; +} diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 0c0258a..08e99fa 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -90,4 +90,24 @@
void unlock_pam_regions(void);
+enum { + TOHM_REG, + MMIOL_REG, + MMCFG_BASE_REG, + MMCFG_LIMIT_REG, + TOLM_REG, + /* NCMEM and ME ranges are mutually exclusive */ + NCMEM_BASE_REG, + NCMEM_LIMIT_REG, + ME_BASE_REG, + ME_LIMIT_REG, + TSEG_BASE_REG, + TSEG_LIMIT_REG, + VTDBAR_REG, + /* Must be last. */ + NUM_MAP_ENTRIES +}; + +int soc_add_dram_resources(struct device *dev, uint64_t mc_values[], int start_index); + #endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a177a89..c700816 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <drivers/ocp/include/vpd.h> #include <soc/acpi.h> +#include <soc/chip_common.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -32,24 +33,6 @@ const char *description; };
-enum { - TOHM_REG, - MMIOL_REG, - MMCFG_BASE_REG, - MMCFG_LIMIT_REG, - TOLM_REG, - /* NCMEM and ME ranges are mutually exclusive */ - NCMEM_BASE_REG, - NCMEM_LIMIT_REG, - ME_BASE_REG, - ME_LIMIT_REG, - TSEG_BASE_REG, - TSEG_LIMIT_REG, - VTDBAR_REG, - /* Must be last. */ - NUM_MAP_ENTRIES -}; - static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"), [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"), @@ -265,50 +248,6 @@ mc_values[TOLM_REG]); LOG_RESOURCE("mmio_tolm", dev, res);
- if (CONFIG(SOC_INTEL_HAS_CXL)) { - /* 4GiB -> CXL Memory */ - uint32_t gi_mem_size; - gi_mem_size = get_generic_initiator_mem_size(); /* unit: 64MB */ - /* - * Memory layout when there is CXL HDM (Host-managed Device Memory): - * -------------- <- TOHM - * CXL memory regions (pds global variable records the base/size of them) - * Processor attached high memory - * -------------- <- 0x100000000 (4GB) - */ - res = upper_ram_end(dev, index++, - mc_values[TOHM_REG] - ((uint64_t)gi_mem_size << 26) + 1); - LOG_RESOURCE("high_ram", dev, res); - - /* CXL Memory */ - uint8_t i; - for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) - continue; - - if (CONFIG(OCP_VPD)) { - unsigned long flags = IORESOURCE_CACHEABLE; - int cxl_mode = get_cxl_mode_from_vpd(); - if (cxl_mode == CXL_SPM) - flags |= IORESOURCE_SOFT_RESERVE; - else - flags |= IORESOURCE_STORED; - - res = fixed_mem_range_flags(dev, index++, - (uint64_t)pds.pds[i].base << 26, - (uint64_t)pds.pds[i].size << 26, flags); - if (cxl_mode == CXL_SPM) - LOG_RESOURCE("specific_purpose_memory", dev, res); - else - LOG_RESOURCE("CXL_memory", dev, res); - } - } - } else { - /* 4GiB -> TOHM */ - res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1); - LOG_RESOURCE("high_ram", dev, res); - } - /* add MMIO CFG resource */ res = mmio_from_to(dev, index++, mc_values[MMCFG_BASE_REG], mc_values[MMCFG_LIMIT_REG] + 1); @@ -331,6 +270,9 @@ res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); LOG_RESOURCE("legacy_write_protect", dev, res);
+ /* Add SoC specific resources */ + index += soc_add_dram_resources(dev, mc_values, index); + *res_count = index; }