Attention is currently required from: Arthur Heymans, Jason Glenesk, Matt DeVillier, Raul Rangel.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75933?usp=email )
Change subject: [UNTESTED] soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75933/comment/48f1d946_5721ab06 :
PS1, Line 12: Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There
: is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO
: device and not a PCI device.
It had Naresh confused too, who wrote code to probe for the device before adding it, which failed an […]
you mean a comment pointing out that this is what the reference code but where i'm not really sure where this is from exactly?
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