Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, coreboot doesn't set UPD FSPS PchPmPwrCycDur (Reset Power Cycle Duration). So, FSP set default value(4sec) to PchPmPwrCycDur. This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur to 1 second to minimize the delay.
System behaviour for Power Cylce or Global Reset: With default value: S0->S3->S5 -> [~5 seconds delay]-> S5->S3->S0
With the change: S0->S3->S5 -> [~2 seconds delay]-> S5->S3->S0
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2d3156a..04221af 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -143,6 +143,7 @@ register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmPwrCycDur" = "1" # 1s
# Enable Audio DSP oscillator qualification for S0ix register "cppmvric2_adsposcdis" = "1"
Sridhar Siricilla has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, coreboot doesn't set UPD FSPS PchPmPwrCycDur (Reset Power Cycle Duration). So, FSP set default value(4sec) to PchPmPwrCycDur. This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur to 1 second to minimize the delay.
System behaviour for Power Cylce or Global Reset: With default value: S0->S3->S5 -> [~5 seconds delay]-> S5->S3->S0
With the change: S0->S3->S5 -> [~2 seconds delay]-> S5->S3->S0
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/2
Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#3).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value(4sec). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur (Reset Power Cycle Duration) to 1sec to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S3->S5 -> [ ~5seconds delay ] -> S5->S3->S0
With the Patch: S0->S3->S5 -> [ ~2seconds delay ] -> S5->S3->S0
Test=Verified on hatch BUG=p:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 3:
(8 comments)
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@9 PS3, Line 9: Currently, Reset Power Cycle Duration is set with default value(4sec). Please add a space before the (, and use SI unit *s*.
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@11 PS3, Line 11: set sets
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@11 PS3, Line 11: 1sec 1 s
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@16 PS3, Line 16: S3 What does S3 have to do with this?
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@16 PS3, Line 16: 5seconds 5 seconds
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@18 PS3, Line 18: Patch patch
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@19 PS3, Line 19: 2seconds 2 seconds
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@22 PS3, Line 22: p *p* or *b*?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@21 PS3, Line 21: Test=Verified on hatch Did you run FAFT test to check the behavior?
Hello Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#4).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value(4sec). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur (Reset Power Cycle Duration) to 1sec to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S3->S5 -> [ ~5seconds delay ] -> S5->S3->S0
With the Patch: S0->S3->S5 -> [ ~2seconds delay ] -> S5->S3->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on hatch BUG=p:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 4:
This latest patchset doesn't set PchPmPwrCycDur
Hello Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#5).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value(4sec). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur (Reset Power Cycle Duration) to 1sec to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S3->S5 -> [ ~5seconds delay ] -> S5->S3->S0
With the Patch: S0->S3->S5 -> [ ~2seconds delay ] -> S5->S3->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on hatch BUG=p:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/5
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@21 PS3, Line 21: Test=Verified on hatch
Did you run FAFT test to check the behavior?
I tested the patch, but I still see the issue(crosbug:158540753). It looks like some delay is required after ec command "powerbtn 200" before triggering ecrst off/ecrst on @CR50 console.
Hello Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#6).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on hatch BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/6
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 6:
(8 comments)
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@9 PS3, Line 9: Currently, Reset Power Cycle Duration is set with default value(4sec).
Please add a space before the (, and use SI unit *s*.
Done
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@11 PS3, Line 11: 1sec
1 s
Done
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@11 PS3, Line 11: set
sets
Done
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@16 PS3, Line 16: 5seconds
5 seconds
Done
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@16 PS3, Line 16: S3
What does S3 have to do with this?
I have just written the system's sleep transition here. Here, S3 state has nothing to do here,
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@18 PS3, Line 18: Patch
patch
Done
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@19 PS3, Line 19: 2seconds
2 seconds
Done
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@22 PS3, Line 22: p
*p* or *b*?
Done
Hello Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#7).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on hatch BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/7
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@21 PS3, Line 21: Test=Verified on hatch
I tested the patch, but I still see the issue(crosbug:158540753). […]
Along with these CL and overriding reset_delay in the FAFT Puff XML, I observe test "platform_ServoPowerStateController_USBPluggedin" is passing now.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 7: Code-Review+1
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/7//COMMIT_MSG@25 PS7, Line 25: Test=Verified on hatch Can you run FAFT on both Puff and Hatch as this commit would impact both however they use different FIT kit revs.
Hello Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#8).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on Hatch and Puff boards BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/8
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42441/10/src/mainboard/google/hatch... PS10, Line 147: #NOTE: Duration programmed in the below register should never be smaller than the : #stretch duration programmed in the following registers - Space after # please
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 10: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 12:
Sridhar, I guess the rebases are because the "Submit" button is missing? There is one comment that is unresolved.
Hello Shelley Chen, V Sowmya, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Edward O'Callaghan, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#13).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on Hatch and Puff boards BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/13
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/3//COMMIT_MSG@21 PS3, Line 21: Test=Verified on hatch
Along with these CL and overriding reset_delay in the FAFT Puff XML, I observe test "platform_ServoP […]
Done
https://review.coreboot.org/c/coreboot/+/42441/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42441/10/src/mainboard/google/hatch... PS10, Line 147: #NOTE: Duration programmed in the below register should never be smaller than the : #stretch duration programmed in the following registers -
Space after # please
Done
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/7//COMMIT_MSG@25 PS7, Line 25: Test=Verified on hatch
Can you run FAFT on both Puff and Hatch as this commit would impact both however they use different […]
I ran FAFT testcase "platform_ServoPowerStateController_USBPluggedin on hatch , I didn't notice any issues. Yet to run full suite on hatch.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 13: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42441/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42441/7//COMMIT_MSG@25 PS7, Line 25: Test=Verified on hatch
I ran FAFT testcase "platform_ServoPowerStateController_USBPluggedin on hatch , I didn't notice any […]
Ack
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 14: Code-Review+2
Hello V Sowmya, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Edward O'Callaghan, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#15).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on Hatch and Puff boards BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/15
Hello V Sowmya, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Edward O'Callaghan, Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42441
to look at the new patch set (#16).
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on Hatch and Puff boards BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/16
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 16: Code-Review+2
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
Patch Set 16: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay.
Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s.
Test=Verified on Hatch and Puff boards BUG=b:158634281
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441 Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-by: V Sowmya v.sowmya@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved V Sowmya: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2d3156a..cb314ab 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -142,7 +142,15 @@ register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms - register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s
# Enable Audio DSP oscillator qualification for S0ix register "cppmvric2_adsposcdis" = "1"