Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63777

to look at the new patch set (#4).

Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
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soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg

Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS
register bit-fields with the W1C attribute.
So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear
SAF_CE (bit 8).

This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include
SAF_CE (bit 8).

BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4 and 8.

Signed-off-by: Subrata Banik 
Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8
---
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/63777/4