New patch to review for coreboot: 55c70fc exynos5250: read product ID register before gating its clock

[David Hendricks]

David Hendricks ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3121

-gerrit

commit 55c70fcfccdf8591af4afc05f8b65b7a955b4ef0
Author: David Hendricks 
Date:   Mon Apr 22 16:03:11 2013 -0700

exynos5250: read product ID register before gating its clock

The product ID comes from a special-function register (SFR) which has
    interesting behavior whereby reading its value causes it to persist
    in memory even after the clock is gated.

The chip ID may be read by the OS kernel; for Linux, it is used while
    decompressing the kernel. So to make this information available after
    coreboot finishes and save a little bit of power we can force a read
    to occur before gating its IP block.

(credit to Gabe for finding symptom in the kernel)

Change-Id: Iaa21e6e718b9000b5558f568020f393779fd208e
    Signed-off-by: Gabe Black 
    Signed-off-by: David Hendricks 
---
 src/cpu/samsung/exynos5250/clock_init.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index c94cadf..2fd9947 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -295,6 +295,7 @@ void system_clock_init(struct mem_timings *mem,
 void clock_gate(void)
 {
    struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	uint32_t chip_id;

/* CLK_GATE_IP_SYSRGT */
    clrbits_le32(&clk->gate_ip_sysrgt, CLK_C2C_MASK);
@@ -427,8 +428,16 @@ void clock_gate(void)
    				  CLK_TZPC3_MASK |
    				  CLK_TZPC2_MASK |
    				  CLK_TZPC1_MASK |
-					  CLK_TZPC0_MASK |
-					  CLK_CHIPID_MASK);
+					  CLK_TZPC0_MASK);
+
+	/*
+	 * Ensure the chip ID is read before gating its IP block. This causes
+	 * the value to remain persistent in memory so when other code
+	 * references the PRO_ID SFR it will identify the chip correctly.
+	 */
+	chip_id = (readl((void *)EXYNOS_PRO_ID) >> 20) & 0xf;
+	if (chip_id == 5)
+		clrbits_le32(&clk->gate_ip_peris, CLK_CHIPID_MASK);

/* CLK_GATE_BLOCK */
    clrbits_le32(&clk->gate_block, CLK_ACP_MASK);