Change in coreboot[master]: soc/amd/stoneyridge: split southbridge code - coreboot-gerrit

16 Dec 2021


      Attention is currently required from: Marshall Dawson, Felix Held.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60142 )
Change subject: soc/amd/stoneyridge: split southbridge code
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Patch Set 1:
(1 comment)
File src/soc/amd/stoneyridge/fch.c:
https://review.coreboot.org/c/coreboot/+/60142/comment/b24621bd_a8ef4534 
PS1, Line 175: 	if (gnvs) {
There's probably no need to have them in GNVS or update on S3 resume path.
So xHCI has to reload firmware from SPI flash on D0 transition?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588
Gerrit-Change-Number: 60142
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