Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38385 )
Change subject: soc/intel/cannonlake: Fix ASL compilation remarks ......................................................................
soc/intel/cannonlake: Fix ASL compilation remarks
This patch fixes below ASL compilation remarks
1. dsdt.asl 495: Method (_DSM, 4) Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator) 2. dsdt.asl 721: Name(GPMB, Package(5) {0}) Remark 2063 - ^ Initializer list shorter than declared package length
Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/scs.asl 2 files changed, 4 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38385/1
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 7702ad5..e2eb78c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -159,7 +159,7 @@ }
/* GPIO Power Management bits */ -Name(GPMB, Package(TOTAL_GPIO_COMM) {0}) +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
/* * Save GPIO Power Management bits diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 0012a4d..4938081 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -107,8 +107,6 @@ If (LEqual (Arg0, ^DSUU)) { /* Check the revision */ If (LGreaterEqual (Arg1, Zero)) { - /* Switch statement based on the function index. */ - Switch (ToInteger (Arg2)) { /* * Function Index 0 the return value is a buffer containing * one bit for each function index, starting with zero. @@ -125,10 +123,9 @@ * For SD we have to support functions to * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] */ - Case (0) { + If (LEqual (Arg2, Zero)) { Return (Buffer () { 0x19 }) } - /* * Function Index 3: Set 1.8v signalling. * We put a sleep of 100ms in this method to @@ -136,7 +133,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - Case (3) { + If (LEqual (Arg2, 3)) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -147,11 +144,10 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - Case (4) { + If (LEqual (Arg2, 4)) { Sleep (100) Return(Buffer () { 0x00 }) } - } } } Return(Buffer() { 0x0 })
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38385 )
Change subject: soc/intel/cannonlake: Fix ASL compilation remarks ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38385 )
Change subject: soc/intel/cannonlake: Fix ASL compilation remarks ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38385 )
Change subject: soc/intel/cannonlake: Fix ASL compilation remarks ......................................................................
soc/intel/cannonlake: Fix ASL compilation remarks
This patch fixes below ASL compilation remarks
1. dsdt.asl 495: Method (_DSM, 4) Remark 2119 - ^ Control Method marked Serialized (Due to use of Switch operator) 2. dsdt.asl 721: Name(GPMB, Package(5) {0}) Remark 2063 - ^ Initializer list shorter than declared package length
Change-Id: Iabd6c39025713dda7aa69cb479f003fbec8855b3 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38385 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lance Zhao lance.zhao@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/scs.asl 2 files changed, 4 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 7702ad5..e2eb78c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -159,7 +159,7 @@ }
/* GPIO Power Management bits */ -Name(GPMB, Package(TOTAL_GPIO_COMM) {0}) +Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
/* * Save GPIO Power Management bits diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 0012a4d..4938081 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -107,8 +107,6 @@ If (LEqual (Arg0, ^DSUU)) { /* Check the revision */ If (LGreaterEqual (Arg1, Zero)) { - /* Switch statement based on the function index. */ - Switch (ToInteger (Arg2)) { /* * Function Index 0 the return value is a buffer containing * one bit for each function index, starting with zero. @@ -125,10 +123,9 @@ * For SD we have to support functions to * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] */ - Case (0) { + If (LEqual (Arg2, Zero)) { Return (Buffer () { 0x19 }) } - /* * Function Index 3: Set 1.8v signalling. * We put a sleep of 100ms in this method to @@ -136,7 +133,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - Case (3) { + If (LEqual (Arg2, 3)) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -147,11 +144,10 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - Case (4) { + If (LEqual (Arg2, 4)) { Sleep (100) Return(Buffer () { 0x00 }) } - } } } Return(Buffer() { 0x0 })
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38385 )
Change subject: soc/intel/cannonlake: Fix ASL compilation remarks ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 0/0/0
Please note: This test is under development and might not be accurate at all!