Attention is currently required from: Pranava Y N, Subrata Banik.
Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84408?usp=email )
Change subject: mb/google/fatcat: Add FW_CONFIG ......................................................................
mb/google/fatcat: Add FW_CONFIG
BUG=b:348678529 TEST=Boot on google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb A src/mainboard/google/fatcat/variants/fatcat/variant.c 5 files changed, 488 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/84408/1
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index a47a2a4..c743249 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -22,6 +22,9 @@ select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI + select FW_CONFIG_SOURCE_VPD select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GENERATE_SMBIOS_TABLES select GOOGLE_SMBIOS_MAINBOARD_VERSION diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk index 4c33dad..2037ae9 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk @@ -4,3 +4,5 @@ romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c new file mode 100644 index 0000000..2e07137 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> +#include <inttypes.h> + +#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) + +static const struct pad_config i2s_enable_pads[] = { + /* Audio: I2S */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), /* I2S0_SCLK_HDR */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), /* I2S0_SFRM_HDR */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), /* I2S0_TXD_HDR */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), /* I2S0_RXD_HDR */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6), /* I2S1_SCLK_HDR */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6), /* I2S1_SFRM_HDR */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6), /* I2S1_TXD_HDR */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6), /* I2S1_RXD_HDR */ + + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), /* DMIC_CLK */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), /* DMIC_DATA */ + + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), /* DMIC_CLK */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), /* DMIC_DATA */ + +}; + +static const struct pad_config hda_enable_pads[] = { + /* Audio: HDA */ + + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1), + + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), /* DMIC_CLK */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), /* DMIC_DATA */ +}; + +static const struct pad_config sndw_enable_pads[] = { + /* Soundwire GPIO Config */ + /* Soundwire - External codec - JE Header */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), /* SNDW3_DATA0 */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), /* SNDW0_CLK */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), /* SNDW0_DATA */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2), /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2), /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), /* SNDW1_DATA*/ + + /* GPP_D13: RST_HP_L*/ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), +}; + +static const struct pad_config sndw_alc722_enable_pads[] = { + /* Soundwire GPIO Config */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), /* SNDW3_DATA0 */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), /* SNDW3_DATA1 */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), /* SNDW3_DATA2 */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), /* DMIC_CLK_A0 */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), /* DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), /* SNDW1_DATA */ + + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), /* DMIC_CLK */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), /* DMIC_DATA */ +}; + +static const struct pad_config audio_disable_pads[] = { + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), + PAD_NC(GPP_D09, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), +}; + +static const struct pad_config pciewlan_disable_pads[] = { + /* GPP_A11: WLAN_RST_N */ + PAD_NC(GPP_A11, NONE), + /* GPP_C13: CLKREQ4_X1_GEN4_M2_WLAN_N */ + PAD_NC(GPP_C13, NONE), + + /* GPP_A12: WIFI_WAKE_N */ + PAD_NC(GPP_A12, NONE) +}; + +static const struct pad_config wwan_disable_pads[] = { + /* GPP_E02: WWAN_WAKE_GPIO_N */ + PAD_NC(GPP_E02, NONE) +}; + +static const struct pad_config x1slot_disable_pads[] = { + /* GPP_B25: X1_SLOT_WAKE_N */ + PAD_NC(GPP_B25, NONE) +}; + +static const struct pad_config cnvi_disable_pads[] = { + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_NC(GPP_F00, NONE), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_NC(GPP_F01, NONE), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_NC(GPP_F02, NONE), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_NC(GPP_F03, NONE), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_NC(GPP_F04, NONE), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_NC(GPP_F05, NONE), + + /* GPP_A16: BT_RF_KILL_N */ + PAD_NC(GPP_A16, NONE), + /* GPP_A17: WIFI_RF_KILL_N */ + PAD_NC(GPP_A17, NONE), +}; + +static const struct pad_config touchpad_i2c5_enable_pads[] = { + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), +}; + +static const struct pad_config touchpad_i2c_disable_pads[] = { + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_NC(GPP_F13, NONE), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_NC(GPP_F18, NONE), +}; + +static const struct pad_config touchscreen_disable_pads[] = { + /* GPP_F08: TCH_PNL1_PWR_EN */ + PAD_CFG_GPO(GPP_F08, 0, PLTRST), + + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */ + PAD_NC(GPP_E13, NONE), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + /* THC NOTE: use GPO instead of GPO for THC0 Rst */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_NC(GPP_E18, NONE), +}; + +static const struct pad_config touchscreen_i2c4_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config touchscreen_thc0i2c_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF1: THC I2C0_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF1: THC I2C0 SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config touchscreen_gspi0_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF5), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF5), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT) +}; + +static const struct pad_config touchscreen_thc0spi_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 NF3: THC HID-SPI */ + /* THC NOTE: use GPO instead of GPO for THC0 Rst */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), +}; + +static const struct pad_config peg_x4slot_wake_disable_pads[] = { + /* GPP_D24: PEG_SLOT_WAKE_N */ + PAD_NC(GPP_D24, NONE), + /* GPP_D25: X4_SLOT_WAKE_N */ + PAD_NC(GPP_D25, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + printk(BIOS_INFO, "FW config 0x%" PRIx64 "\n", fw_config_get()); + if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { + printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(AUDIO,PTL_ALC1019_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO,PTL_ALC5682I_MAX9857A_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO,PTL_MAX98360_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, PTL_MAX98373_ALC5682_SNDW))) { + printk(BIOS_INFO, "Configure GPIOs for SoundWire audio (ext codec).\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_enable_pads); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, PTL_ALC722_SNDW))) { + printk(BIOS_INFO, "Configure GPIOs for SoundWire audio (onboard codec).\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, PTL_ALC256_HDA))) { + printk(BIOS_INFO, "Configure GPIOs for ALC256 HDA audio.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads); + } + + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI))) { + GPIO_PADBASED_OVERRIDE(padbased_table, pciewlan_disable_pads); + } else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE))) { + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(WWAN, PCIE))) { + + } else if (fw_config_probe(FW_CONFIG(WWAN, USB))) { + // TODO: not supported at this time + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(X1SLOT, SD)) || + fw_config_probe(FW_CONFIG(X1SLOT, ETH))) { + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(TOUCHPAD, I2C5_HYNITRON))) { + GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c5_enable_pads); + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, THC1I2C_HYNITRON))) { + // TODO: THC-I2C + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, I2C4))) { + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_i2c4_enable_pads); + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, THC0_I2C))) { + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc0i2c_enable_pads); + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, GSPI0))) { + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi0_enable_pads); + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, THC0_SPI))) { + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc0spi_enable_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads); + } + + // NOTE: disable peg and x4 slot wake for now + GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); +} diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index fc406a2..6edba81 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -1,3 +1,59 @@ +fw_config + field DEBUG 0 1 + option NONE 0 + option RMT 1 + end + field AUDIO 8 10 + option NONE 0 + option PTL_ALC1019_ALC5682I_I2S 1 + option PTL_MAX98373_ALC5682_SNDW 2 + option PTL_ALC722_SNDW 3 + option PTL_ALC5682I_MAX9857A_I2S 4 + option PTL_ALC256_HDA 5 + option PTL_MAX98360_ALC5682I_I2S 6 + end + field WIFI 11 + option WIFI_CNVI 0 + option WIFI_PCIE 1 + end + field TOUCHSCREEN 12 14 + option NONE 0 + option I2C4 1 + option GSPI0 2 + option THC0_SPI 3 + option THC0_I2C 4 + end + field TOUCHPAD 16 18 + option NONE 0 + option THC1I2C_HYNITRON 1 + option I2C5_HYNITRON 2 + end + field X1SLOT 19 20 + option NONE 0 + option SD 1 + option ETH 2 + end + field STORAGE 21 22 + option TOP_NVME 0 # RP5 + option BOTTOM_NVME 1 # RP9 + option UFS 2 + end + field FPS 23 24 + option NONE 0 + option SPI 1 + option USB2 2 + end + field WWAN 25 26 + option NONE 0 + option PCIE 1 + option USB 2 + end + field CNVI_BT 27 + option BT_USB 0 + option BT_PCIE 1 + end +end + chip soc/intel/pantherlake
# GPE configuration @@ -154,7 +210,10 @@
device ref heci1 on end
- device ref thc0 on end + device ref thc0 on + probe TOUCHSCREEN THC0_SPI + probe TOUCHSCREEN THC0_I2C + end device ref thc1 off end
device ref tbt_pcie_rp0 on end @@ -251,6 +310,7 @@ # }" end # Gbe device ref pcie_rp2 on + probe WWAN PCIE register "pcie_rp[PCIE_RP(2)]" = "{ .clk_src = 5, .clk_req = 5, @@ -258,6 +318,8 @@ }" end # WWAN device ref pcie_rp3 on + probe X1SLOT SD + probe X1SLOT ETH # Enable PCH PCIE x1 slot using CLK 3 register "pcie_rp[PCIE_RP(3)]" = "{ .clk_src = 2, @@ -270,10 +332,14 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" register "reset_delay_ms" = "20" register "srcclk_pin" = "2" - device generic 0 on end + device generic 0 on + probe X1SLOT SD + probe X1SLOT ETH + end end end # PCIE x1 slot device ref pcie_rp4 on + probe WIFI WIFI_PCIE register "pcie_rp[PCH_RP(4)]" = "{ .clk_src = 4, .clk_req = 4, @@ -282,10 +348,13 @@ chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" register "srcclk_pin" = "4" - device pci 00.0 on end + device pci 00.0 on + probe WIFI WIFI_PCIE + end end end # discrete WLAN device ref pcie_rp5 on + probe STORAGE TOP_NVME register "pcie_rp[PCIE_RP(5)]" = "{ .clk_src = 6, .clk_req = 6, @@ -303,6 +372,7 @@ device ref pcie_rp7 off end device ref pcie_rp8 off end device ref pcie_rp9 on + probe STORAGE BOTTOM_NVME register "pcie_rp[PCIE_RP(9)]" = "{ .clk_src = 1, .clk_req = 1, @@ -400,14 +470,19 @@ end
device ref cnvi_wifi on + probe WIFI WIFI_CNVI chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" - device generic 0 on end + device generic 0 on + probe WIFI WIFI_CNVI + end end end # CNVi - device ref cnvi_bluetooth on end # CNVi BT + device ref cnvi_bluetooth on + probe CNVI_BT BT_PCIE + end # CNVi BT
device ref i2c0 on end device ref i2c1 on @@ -554,7 +629,10 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO PTL_ALC1019_ALC5682I_I2S + probe AUDIO PTL_ALC5682I_MAX9857A_I2S + end end chip drivers/i2c/generic register "hid" = ""RTL5682"" @@ -566,7 +644,9 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO PTL_MAX98360_ALC5682I_I2S + end end
# Ref config #5 for Chrome, transducer card config 5A @@ -582,25 +662,33 @@ register "hid" = ""10EC1019"" register "desc" = ""Realtek SPK AMP L"" register "uid" = "0" - device i2c 28 on end + device i2c 28 on + probe AUDIO PTL_ALC1019_ALC5682I_I2S + end end chip drivers/i2c/generic register "hid" = ""10EC1019"" register "desc" = ""Realtek SPK AMP R"" register "uid" = "1" - device i2c 29 on end + device i2c 29 on + probe AUDIO PTL_ALC1019_ALC5682I_I2S + end end chip drivers/i2c/generic register "hid" = ""10EC1019"" register "desc" = ""Realtek SPK AMP TL"" register "uid" = "2" - device i2c 2a on end + device i2c 2a on + probe AUDIO PTL_ALC1019_ALC5682I_I2S + end end chip drivers/i2c/generic register "hid" = ""10EC1019"" register "desc" = ""Realtek SPK AMP TR"" register "uid" = "3" - device i2c 2b on end + device i2c 2b on + probe AUDIO PTL_ALC1019_ALC5682I_I2S + end end chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -609,6 +697,7 @@ end end #i2c3 device ref i2c4 on + probe TOUCHSCREEN I2C4 chip drivers/i2c/hid register "generic.hid" = ""ELAN6918"" register "generic.desc" = ""ELAN Touchscreen"" @@ -621,10 +710,13 @@ register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 16 on end + device i2c 16 on + probe TOUCHSCREEN I2C4 + end end end device ref i2c5 on + probe TOUCHPAD I2C5_HYNITRON chip drivers/i2c/hid register "generic.hid" = ""HFW68H"" register "generic.desc" = ""Hynitron TOUCHPAD"" @@ -632,7 +724,9 @@ register "generic.uid" = "5" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end + device i2c 2c on + probe TOUCHPAD I2C5_HYNITRON + end end end # i2c5
@@ -640,7 +734,9 @@ device ref uart1 off end device ref uart2 off end
- device ref gspi0 on end + device ref gspi0 on + probe TOUCHSCREEN GSPI0 + end device ref gspi1 on end
device ref smbus on end @@ -657,7 +753,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 1 ID 1 register "desc" = ""Headset Codec"" - device generic 1.1 on end + device generic 1.1 on + probe AUDIO PTL_ALC722_SNDW + end end end end @@ -665,13 +763,17 @@ register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" register "sdmode_delay" = "5" - device generic 0 on end + device generic 0 on + probe AUDIO PTL_ALC5682I_MAX9857A_I2S + end end chip drivers/generic/max98357a register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" register "sdmode_delay" = "5" - device generic 0 on end + device generic 0 on + probe AUDIO PTL_MAX98360_ALC5682I_I2S + end end end
diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c new file mode 100644 index 0000000..d6fc711 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <fw_config.h> + +void variant_update_soc_chip_config(config_t *config) +{ + /* CNVi */ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI))) { + config->cnvi_wifi_core = true; + config->cnvi_bt_core = true; + config->pcie_rp[PCIE_RP(4)].flags = PCIE_RP_CLK_SRC_UNUSED; + config->pcie_clk_config_flag[4] = 0; + + if (fw_config_probe(FW_CONFIG(CNVI_BT, BT_PCIE))) { + config->usb2_ports[7].enable = 0; + config->usb2_ports[7].ocpin = OC_SKIP; + config->usb2_ports[7].tx_bias = USB2_BIAS_0MV; + config->usb2_ports[7].tx_emp_enable = USB2_EMP_OFF; + config->usb2_ports[7].pre_emp_bias = USB2_BIAS_0MV; + config->usb2_ports[7].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; + } + /* discrete */ + } else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE))) { + config->cnvi_wifi_core = false; + config->cnvi_bt_core = false; + config->cnvi_bt_audio_offload = 0; + } else { + config->pcie_rp[PCIE_RP(4)].flags = PCIE_RP_CLK_SRC_UNUSED; + config->pcie_clk_config_flag[4] = 0; + } +}
-
Jérémy Compostella (Code Review)