Patch set updated for coreboot: 8293c23 tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.
Isaac Christensen (isaac.christensen@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6702
-gerrit
commit 8293c239f1554ebebc29acacc0f261ed5d1a09ee Author: Gabe Black gabeblack@google.com Date: Thu Oct 3 04:35:01 2013 -0700
tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.
The pins on tegra are controlled by three different units, the pinmux, the pin group controls, and the GPIO banks. Each of these units controls some aspect of the pins, and they layer together and interact in interesting ways.
By default, the GPIOs are configured to pass through the special purpose IO that the pinmux is configured to and so can be ignored unless a GPIO is needed. The pinmux controls which special purpose signal passes through, along with pull ups, downs, and whether the output is tristated. The pingroup controls change the parameters of a group of pins which all have to do with a related function unit.
The enum which holds constants related to the pinmux is relatively involved and may not be entirely complete or correct due to slightly inconsistent, incomplete, or missing documentation related to the pinmux. Considerable effort has been made to make it as accurate as possible. It includes a constant which is the index into the pinmux control registers for that pin, what each of the functions supported by that pin are, and which GPIO it corresponds to. The GPIO constant is named after the GPIO and is the pinmux register index for the pin for that GPIO. That way, when you need to turn on a GPIO, you can use that constant along with the pinmux manipulating functions to enable its tristate and pull up/down mode in addition to setting up the GPIO controls.
Also, while in general I prefer not to use macros or the preprocessor when writing C code, in this case the set of constants in the enums was too large and cumbersome to manage without them. Since they're being used to construct a table in a straightforward way, hopefully their negative aspects will be minimized.
In addition to the low level functions in each driver, the GPIO code also includes some high level functions to set up input or output GPIOs since that will probably be a very common thing to want to do.
Old-Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d Signed-off-by: Gabe Black gabeblack@google.com Reviewed-on: https://chromium-review.googlesource.com/171806 Reviewed-by: Ronald Minnich rminnich@chromium.org Reviewed-by: David Hendricks dhendrix@chromium.org Commit-Queue: Gabe Black gabeblack@chromium.org Tested-by: Gabe Black gabeblack@chromium.org (cherry picked from commit 5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a)
tegra124: Add base address for the pinmux and pingroup registers.
There weren't any constants for the pinmux or pingroup registers in the address map header.
Old-Change-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe Signed-off-by: Gabe Black gabeblack@google.com Reviewed-on: https://chromium-review.googlesource.com/172081 Reviewed-by: Julius Werner jwerner@chromium.org Tested-by: Gabe Black gabeblack@chromium.org Commit-Queue: Gabe Black gabeblack@chromium.org (cherry picked from commit 79b61016bfd702b0ea5221658305d8bd359f4f62)
Squashed two related commits.
Change-Id: Ifeb6085128bd53f0ef5f82c930eda66a2b59499b Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com --- src/soc/nvidia/tegra/gpio.c | 240 +++++++++++++++++++++ src/soc/nvidia/tegra/gpio.h | 63 ++++++ src/soc/nvidia/tegra/pingroup.c | 35 +++ src/soc/nvidia/tegra/pingroup.h | 43 ++++ src/soc/nvidia/tegra/pinmux.c | 35 +++ src/soc/nvidia/tegra/pinmux.h | 44 ++++ src/soc/nvidia/tegra124/Makefile.inc | 3 + src/soc/nvidia/tegra124/gpio.h | 67 ++++++ src/soc/nvidia/tegra124/include/soc/addressmap.h | 2 + src/soc/nvidia/tegra124/pingroup.h | 67 ++++++ src/soc/nvidia/tegra124/pinmux.h | 260 +++++++++++++++++++++++ 11 files changed, 859 insertions(+)
diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c new file mode 100644 index 0000000..d4b5bdd --- /dev/null +++ b/src/soc/nvidia/tegra/gpio.c @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <stddef.h> +#include <stdint.h> + +#include "gpio.h" +#include "pinmux.h" + +static void gpio_input_common(int gpio_index, int pinmux_index, + uint32_t pconfig) +{ + pconfig |= PINMUX_INPUT_ENABLE; + gpio_set_int_enable(gpio_index, 0); + gpio_set_mode(gpio_index, GPIO_MODE_GPIO); + gpio_set_out_enable(gpio_index, 0); + pinmux_set_config(pinmux_index, pconfig); +} + +void gpio_input(int gpio_index, int pinmux_index) +{ + gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_NONE); +} + +void gpio_input_pullup(int gpio_index, int pinmux_index) +{ + gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_UP); +} + +void gpio_input_pulldown(int gpio_index, int pinmux_index) +{ + gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_DOWN); +} + +void gpio_output(int gpio_index, int pinmux_index, int value) +{ + uint32_t pconfig = PINMUX_PULL_NONE; + + pinmux_set_config(pinmux_index, pconfig | PINMUX_TRISTATE); + gpio_set_int_enable(gpio_index, 0); + gpio_set_mode(gpio_index, GPIO_MODE_GPIO); + gpio_set_out_enable(gpio_index, 1); + gpio_set_out_value(gpio_index, value); + pinmux_set_config(pinmux_index, pconfig); +} + +enum { + GPIO_GPIOS_PER_PORT = 8, + GPIO_PORTS_PER_BANK = 4, + GPIO_BANKS = 8, + + GPIO_GPIOS_PER_BANK = GPIO_GPIOS_PER_PORT * GPIO_PORTS_PER_BANK, + GPIO_GPIOS = GPIO_BANKS * GPIO_GPIOS_PER_BANK +}; + +struct gpio_bank { + // Values + uint32_t config[GPIO_PORTS_PER_BANK]; + uint32_t out_enable[GPIO_PORTS_PER_BANK]; + uint32_t out_value[GPIO_PORTS_PER_BANK]; + uint32_t in_value[GPIO_PORTS_PER_BANK]; + uint32_t int_status[GPIO_PORTS_PER_BANK]; + uint32_t int_enable[GPIO_PORTS_PER_BANK]; + uint32_t int_level[GPIO_PORTS_PER_BANK]; + uint32_t int_clear[GPIO_PORTS_PER_BANK]; + + // Masks + uint32_t config_mask[GPIO_PORTS_PER_BANK]; + uint32_t out_enable_mask[GPIO_PORTS_PER_BANK]; + uint32_t out_value_mask[GPIO_PORTS_PER_BANK]; + uint32_t in_value_mask[GPIO_PORTS_PER_BANK]; + uint32_t int_status_mask[GPIO_PORTS_PER_BANK]; + uint32_t int_enable_mask[GPIO_PORTS_PER_BANK]; + uint32_t int_level_mask[GPIO_PORTS_PER_BANK]; + uint32_t int_clear_mask[GPIO_PORTS_PER_BANK]; +}; + +static const struct gpio_bank *gpio_banks = (void *)TEGRA_GPIO_BASE; + +static uint32_t gpio_read_port(int index, size_t offset) +{ + int bank = index / GPIO_GPIOS_PER_BANK; + int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; + + return read32((uint8_t *)&gpio_banks[bank] + offset + + port * sizeof(uint32_t)); +} + +static void gpio_write_port(int index, size_t offset, + uint32_t mask, uint32_t value) +{ + int bank = index / GPIO_GPIOS_PER_BANK; + int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; + + uint32_t reg = read32((uint8_t *)&gpio_banks[bank] + offset + + port * sizeof(uint32_t)); + uint32_t new_reg = (reg & ~mask) | (value & mask); + + if (new_reg != reg) { + write32(new_reg, (uint8_t *)&gpio_banks[bank] + offset + + port * sizeof(uint32_t)); + } +} + +void gpio_set_mode(int gpio_index, enum gpio_mode mode) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + 1 << bit, mode ? (1 << bit) : 0); +} + +int gpio_get_mode(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, config)); + return (port & (1 << bit)) != 0; +} + +void gpio_set_lock(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + 1 << bit, 1 << bit); +} + +int gpio_get_lock(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, config)); + return (port & (1 << bit)) != 0; +} + +void gpio_set_out_enable(int gpio_index, int enable) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_enable), + 1 << bit, enable ? (1 << bit) : 0); +} + +int gpio_get_out_enable(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, out_enable)); + return (port & (1 << bit)) != 0; +} + +void gpio_set_out_value(int gpio_index, int value) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_value), + 1 << bit, value ? (1 << bit) : 0); +} + +int gpio_get_out_value(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, out_value)); + return (port & (1 << bit)) != 0; +} + +int gpio_get_in_value(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, in_value)); + return (port & (1 << bit)) != 0; +} + +int gpio_get_int_status(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, int_status)); + return (port & (1 << bit)) != 0; +} + +void gpio_set_int_enable(int gpio_index, int enable) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_enable), + 1 << bit, enable ? (1 << bit) : 0); +} + +int gpio_get_int_enable(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, int_enable)); + return (port & (1 << bit)) != 0; +} + +void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t value = (high_rise ? (0x000001 << bit) : 0) | + (edge ? (0x000100 << bit) : 0) | + (delta ? (0x010000 << bit) : 0); + gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + 0x010101 << bit, value); +} + +void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + uint32_t port = gpio_read_port(gpio_index, + offsetof(struct gpio_bank, int_level)); + *high_rise = ((port & (0x000001 << bit)) != 0); + *edge = ((port & (0x000100 << bit)) != 0); + *delta = ((port & (0x010000 << bit)) != 0); +} + +void gpio_set_int_clear(int gpio_index) +{ + int bit = gpio_index % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_clear), + 1 << bit, 1 << bit); +} diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h new file mode 100644 index 0000000..b62dc90 --- /dev/null +++ b/src/soc/nvidia/tegra/gpio.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA_GPIO_H__ +#define __SOC_NVIDIA_TEGRA_GPIO_H__ + +#include <stdint.h> + +/* Higher level functions for common GPIO configurations. */ + +void gpio_input(int gpio_index, int pinmux_index); +void gpio_input_pullup(int gpio_index, int pinmux_index); +void gpio_input_pulldown(int gpio_index, int pinmux_index); +void gpio_output(int gpio_index, int pinmux_index, int value); + +/* Functions to modify specific GPIO control values. */ + +enum gpio_mode { + GPIO_MODE_SPIO = 0, + GPIO_MODE_GPIO = 1 +}; +void gpio_set_mode(int gpio_index, enum gpio_mode); +int gpio_get_mode(int gpio_index); + +// Lock a GPIO with extreme caution since they can't be unlocked. +void gpio_set_lock(int gpio_index); +int gpio_get_lock(int gpio_index); + +void gpio_set_out_enable(int gpio_index, int enable); +int gpio_get_out_enable(int gpio_index); + +void gpio_set_out_value(int gpio_index, int value); +int gpio_get_out_value(int gpio_index); + +int gpio_get_in_value(int gpio_index); + +int gpio_get_int_status(int gpio_index); + +void gpio_set_int_enable(int gpio_index, int enable); +int gpio_get_int_enable(int gpio_index); + +void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta); +void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta); + +void gpio_set_int_clear(int gpio_index); + +#endif /* __SOC_NVIDIA_TEGRA_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c new file mode 100644 index 0000000..858cb44 --- /dev/null +++ b/src/soc/nvidia/tegra/pingroup.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/addressmap.h> + +#include "pingroup.h" + +static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE; + +void pingroup_set_config(int group_index, uint32_t config) +{ + write32(config, &pingroup_regs[group_index]); +} + +uint32_t pingroup_get_config(int group_index) +{ + return read32(&pingroup_regs[group_index]); +} diff --git a/src/soc/nvidia/tegra/pingroup.h b/src/soc/nvidia/tegra/pingroup.h new file mode 100644 index 0000000..f04b665 --- /dev/null +++ b/src/soc/nvidia/tegra/pingroup.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA_PINGROUP_H__ +#define __SOC_NVIDIA_TEGRA_PINGROUP_H__ + +#include <stdint.h> + +void pingroup_set_config(int group_index, uint32_t config); +uint32_t pingroup_get_config(int group_index); + +enum { + PINGROUP_HSM = 1 << 2, + PINGROUP_SCHMT = 1 << 3, + PINGROUP_LPMD_SHIFT = 4, + PINGROUP_LPMD_MASK = 3 << 4, + PINGROUP_DRVDN_SHIFT = 12, + PINGROUP_DRVDN_MASK = 0x7f << 12, + PINGROUP_DRVUP_SHIFT = 20, + PINGROUP_DRVUP_MASK = 0x7f << 20, + PINGROUP_SLWR_SHIFT = 28, + PINGROUP_SLWR_MASK = 0x3 << 28, + PINGROUP_SLWF_SHIFT = 30, + PINGROUP_SLWF_MASK = 0x3 << 30 +}; + +#endif /* __SOC_NVIDIA_TEGRA_PINGROUP_H__ */ diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c new file mode 100644 index 0000000..6e4b3ff --- /dev/null +++ b/src/soc/nvidia/tegra/pinmux.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/addressmap.h> + +#include "pinmux.h" + +static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE; + +void pinmux_set_config(int pin_index, uint32_t config) +{ + write32(config, &pinmux_regs[pin_index]); +} + +uint32_t pinmux_get_config(int pin_index) +{ + return read32(&pinmux_regs[pin_index]); +} diff --git a/src/soc/nvidia/tegra/pinmux.h b/src/soc/nvidia/tegra/pinmux.h new file mode 100644 index 0000000..e42135d --- /dev/null +++ b/src/soc/nvidia/tegra/pinmux.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA_PINMUX_H__ +#define __SOC_NVIDIA_TEGRA_PINMUX_H__ + +#include <stdint.h> + +void pinmux_set_config(int pin_index, uint32_t config); +uint32_t pinmux_get_config(int pin_index); + +enum { + PINMUX_FUNC_MASK = 3 << 0, + + PINMUX_PULL_MASK = 3 << 2, + PINMUX_PULL_NONE = 0 << 2, + PINMUX_PULL_DOWN = 1 << 2, + PINMUX_PULL_UP = 2 << 2, + + PINMUX_TRISTATE = 1 << 4, + PINMUX_INPUT_ENABLE = 1 << 5, + PINMUX_OPEN_DRAIN = 1 << 6, + PINMUX_LOCK = 1 << 7, + PINMUX_IO_RESET = 1 << 8, + PINMUX_RCV_SEL = 1 << 9 +}; + +#endif /* __SOC_NVIDIA_TEGRA_PINMUX_H__ */ diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index aa35b48..683d940 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -3,6 +3,9 @@ CBOOTIMAGE = cbootimage bootblock-y += cbfs.c bootblock-y += clock.c bootblock-y += monotonic_timer.c +bootblock-y += ../tegra/gpio.c +bootblock-y += ../tegra/pingroup.c +bootblock-y += ../tegra/pinmux.c bootblock-y += timer.c
romstage-y += cbfs.c diff --git a/src/soc/nvidia/tegra124/gpio.h b/src/soc/nvidia/tegra124/gpio.h new file mode 100644 index 0000000..83d727d --- /dev/null +++ b/src/soc/nvidia/tegra124/gpio.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_GPIO_H__ +#define __SOC_NVIDIA_TEGRA124_GPIO_H__ + +#include <soc/nvidia/tegra/gpio.h> +#include <stdint.h> + +/* GPIO index constants. */ + +#define GPIO_PORT_CONSTANTS(port) \ + GPIO_##port##0, GPIO_##port##1, GPIO_##port##2, GPIO_##port##3, \ + GPIO_##port##4, GPIO_##port##5, GPIO_##port##6, GPIO_##port##7 + +enum { + GPIO_PORT_CONSTANTS(A), + GPIO_PORT_CONSTANTS(B), + GPIO_PORT_CONSTANTS(C), + GPIO_PORT_CONSTANTS(D), + GPIO_PORT_CONSTANTS(E), + GPIO_PORT_CONSTANTS(F), + GPIO_PORT_CONSTANTS(G), + GPIO_PORT_CONSTANTS(H), + GPIO_PORT_CONSTANTS(I), + GPIO_PORT_CONSTANTS(J), + GPIO_PORT_CONSTANTS(K), + GPIO_PORT_CONSTANTS(L), + GPIO_PORT_CONSTANTS(M), + GPIO_PORT_CONSTANTS(N), + GPIO_PORT_CONSTANTS(O), + GPIO_PORT_CONSTANTS(P), + GPIO_PORT_CONSTANTS(Q), + GPIO_PORT_CONSTANTS(R), + GPIO_PORT_CONSTANTS(S), + GPIO_PORT_CONSTANTS(T), + GPIO_PORT_CONSTANTS(U), + GPIO_PORT_CONSTANTS(V), + GPIO_PORT_CONSTANTS(W), + GPIO_PORT_CONSTANTS(X), + GPIO_PORT_CONSTANTS(Y), + GPIO_PORT_CONSTANTS(Z), + GPIO_PORT_CONSTANTS(AA), + GPIO_PORT_CONSTANTS(BB), + GPIO_PORT_CONSTANTS(CC), + GPIO_PORT_CONSTANTS(DD), + GPIO_PORT_CONSTANTS(EE), + GPIO_PORT_CONSTANTS(FF) +}; + +#endif /* __SOC_NVIDIA_TEGRA124_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index edacf15..2fd607d 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -36,6 +36,8 @@ enum { TEGRA_EVP_BASE = 0x6000F000, TEGRA_APB_MISC_BASE = 0x70000000, TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, + TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, + TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, diff --git a/src/soc/nvidia/tegra124/pingroup.h b/src/soc/nvidia/tegra124/pingroup.h new file mode 100644 index 0000000..ed9557b --- /dev/null +++ b/src/soc/nvidia/tegra124/pingroup.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_PINGROUP_H__ +#define __SOC_NVIDIA_TEGRA124_PINGROUP_H__ + +#include <soc/nvidia/tegra/pingroup.h> +#include <stdint.h> + +enum { + PINGROUP_AO1_INDEX = 0, /* offset 0x868 */ + PINGROUP_AO2_INDEX = 1, + PINGROUP_AT1_INDEX = 2, + PINGROUP_AT2_INDEX = 3, + PINGROUP_AT3_INDEX = 4, + PINGROUP_AT4_INDEX = 5, + PINGROUP_AT5_INDEX = 6, + PINGROUP_CDEV1_INDEX = 7, + PINGROUP_CDEV2_INDEX = 8, + PINGROUP_DAP1_INDEX = 10, /* offset 0x890 */ + PINGROUP_DAP2_INDEX = 11, + PINGROUP_DAP3_INDEX = 12, + PINGROUP_DAP4_INDEX = 13, + PINGROUP_DBG_INDEX = 14, + PINGROUP_SDIO3_INDEX = 18, /* offset 0x8B0 */ + PINGROUP_SPI_INDEX = 19, + PINGROUP_UAA_INDEX = 20, + PINGROUP_UAB_INDEX = 21, + PINGROUP_UART2_INDEX = 22, + PINGROUP_UART3_INDEX = 23, + PINGROUP_SDIO1_INDEX = 33, /* offset 0x8EC */ + PINGROUP_DDC_INDEX = 37, /* offset 0x8FC */ + PINGROUP_GMA_INDEX = 38, + PINGROUP_GME_INDEX = 42, /* offset 0x910 */ + PINGROUP_GMF_INDEX = 43, + PINGROUP_GMG_INDEX = 44, + PINGROUP_GMH_INDEX = 45, + PINGROUP_OWR_INDEX = 46, + PINGROUP_UAD_INDEX = 47, + PINGROUP_DEV3_INDEX = 49, /* offset 0x92c */ + PINGROUP_CEC_INDEX = 52, /* offset 0x938 */ + PINGROUP_AT6_INDEX = 75, /* offset 0x994 */ + PINGROUP_DAP5_INDEX = 76, + PINGROUP_VBUS_INDEX = 77, + PINGROUP_AO3_INDEX = 78, + PINGROUP_HVC_INDEX = 79, + PINGROUP_SDIO4_INDEX = 80, + PINGROUP_AO0_INDEX = 81, +}; + +#endif /* __SOC_NVIDIA_TEGRA124_PINGROUP_H__ */ diff --git a/src/soc/nvidia/tegra124/pinmux.h b/src/soc/nvidia/tegra124/pinmux.h new file mode 100644 index 0000000..3c275b6 --- /dev/null +++ b/src/soc/nvidia/tegra124/pinmux.h @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_PINMUX_H__ +#define __SOC_NVIDIA_TEGRA124_PINMUX_H__ + +#include <soc/nvidia/tegra/pinmux.h> +#include <stdint.h> + +#define PINMUX_CONSTANTS(index, name, gpio, func0, func1, func2, func3) \ + PINMUX_##name##_INDEX = index, \ + PINMUX_##name##_FUNC_##func0 = 0, \ + PINMUX_##name##_FUNC_##func1 = 1, \ + PINMUX_##name##_FUNC_##func2 = 2, \ + PINMUX_##name##_FUNC_##func3 = 3, \ + PINMUX_GPIO_##gpio = PINMUX_##name##_INDEX + +enum { + PINMUX_CONSTANTS(0, ULPI_DATA0, O1, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(1, ULPI_DATA1, O2, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(2, ULPI_DATA2, O3, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(3, ULPI_DATA3, O4, SPI3, HSI, UA3, ULPI), + PINMUX_CONSTANTS(4, ULPI_DATA4, O5, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(5, ULPI_DATA5, O6, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(6, ULPI_DATA6, O7, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(7, ULPI_DATA7, O0, SPI2, HSI, UA3, ULPI), + PINMUX_CONSTANTS(8, ULPI_CLK, Y0, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(9, ULPI_DIR, Y1, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(10, ULPI_NXT, Y2, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(11, ULPI_STP, Y3, SPI1, SPI5, UD3, ULPI), + PINMUX_CONSTANTS(12, DAP3_FS, P0, I2S2, SPI5, DCA, DCB), + PINMUX_CONSTANTS(13, DAP3_DIN, P1, I2S2, SPI5, DCA, DCB), + PINMUX_CONSTANTS(14, DAP3_DOUT, P2, I2S2, SPI5, DCA, RES3), + PINMUX_CONSTANTS(15, DAP3_SCLK, P3, I2S2, SPI5, RES2, DCB), + PINMUX_CONSTANTS(16, GPIO_PV0, V0, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(17, GPIO_PV1, V1, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(18, SDMMC1_CLK, Z0, SDMMC1, CLK12M, RES2, RES3), + PINMUX_CONSTANTS(19, SDMMC1_CMD, Z1, SDMMC1, SPDIF, SPI4, UA3), + PINMUX_CONSTANTS(20, SDMMC1_DAT3, Y4, SDMMC1, SPDIF, SPI4, UA3), + PINMUX_CONSTANTS(21, SDMMC1_DAT2, Y5, SDMMC1, PM3, SPI4, UA3), + PINMUX_CONSTANTS(22, SDMMC1_DAT1, Y6, SDMMC1, PM3, SPI4, UA3), + PINMUX_CONSTANTS(23, SDMMC1_DAT0, Y7, SDMMC1, RES1, SPI4, UA3), + PINMUX_CONSTANTS(26, CLK2_OUT, W5, EXTPERIPH2, RES1, RES2, RES3), + PINMUX_CONSTANTS(27, CLK2_REQ, CC5, DAP, RES1, RES2, RES3), + PINMUX_CONSTANTS(68, HDMI_INT, N7, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(69, DDC_SCL, V4, I2C4, RES1, RES2, RES3), + PINMUX_CONSTANTS(70, DDC_SDA, V5, I2C4, RES1, RES2, RES3), + PINMUX_CONSTANTS(89, UART2_RXD, C3, IR3, SPDIF, UA3, SPI4), + PINMUX_CONSTANTS(90, UART2_TXD, C2, IR3, SPDIF, UA3, SPI4), + PINMUX_CONSTANTS(91, UART2_RTS_N, J6, UA3, UB3, NOR, SPI4), + PINMUX_CONSTANTS(92, UART2_CTS_N, J5, UA3, UB3, NOR, SPI4), + PINMUX_CONSTANTS(93, UART3_TXD, W6, UC3, RES1, NOR, SPI4), + PINMUX_CONSTANTS(94, UART3_RXD, W7, UC3, RES1, NOR, SPI4), + PINMUX_CONSTANTS(95, UART3_CTS_N, A1, UC3, SDMMC1, DTV, NOR), + PINMUX_CONSTANTS(96, UART3_RTS_N, C0, UC3, PM3, DTV, NOR), + PINMUX_CONSTANTS(97, GPIO_PU0, U0, OWR, UA3, NOR, RES3), + PINMUX_CONSTANTS(98, GPIO_PU1, U1, RES0, UA3, NOR, RES3), + PINMUX_CONSTANTS(99, GPIO_PU2, U2, RES0, UA3, NOR, RES3), + PINMUX_CONSTANTS(100, GPIO_PU3, U3, PM3, UA3, NOR, DCB), + PINMUX_CONSTANTS(101, GPIO_PU4, U4, PM3, UA3, NOR, DCB), + PINMUX_CONSTANTS(102, GPIO_PU5, U5, PM3, UA3, NOR, DCB), + PINMUX_CONSTANTS(103, GPIO_PU6, U6, PM3, UA3, RES2, NOR), + PINMUX_CONSTANTS(104, GEN1_I2C_SDA, C5, I2C1, RES1, RES2, RES3), + PINMUX_CONSTANTS(105, GEN1_I2C_SCL, C4, I2C1, RES1, RES2, RES3), + PINMUX_CONSTANTS(106, DAP4_FS, P4, I2S3, NOR, DTV, RES3), + PINMUX_CONSTANTS(107, DAP4_DIN, P5, I2S3, NOR, RES2, RES3), + PINMUX_CONSTANTS(108, DAP4_DOUT, P6, I2S3, NOR, DTV, RES3), + PINMUX_CONSTANTS(109, DAP4_SCLK, P7, I2S3, NOR, RES2, RES3), + PINMUX_CONSTANTS(110, CLK3_OUT, EE0, EXTPERIPH3, RES1, RES2, RES3), + PINMUX_CONSTANTS(111, CLK3_REQ, EE1, DEV3, RES1, RES2, RES3), + PINMUX_CONSTANTS(112, GPIO_PC7, C7, RES0, RES1, NOR_WP_N, NOR_INT1), + PINMUX_CONSTANTS(113, GPIO_PI5, I5, SDMMC2, RES1, NOR, RES3), + PINMUX_CONSTANTS(114, GPIO_PI7, I7, RES0, TRACE, NOR, DTV), + PINMUX_CONSTANTS(115, GPIO_PK0, K0, RES0, SDMMC3, NOR, SOC_THERM), + PINMUX_CONSTANTS(116, GPIO_PK1, K1, SDMMC2, TRACE, NOR, RES3), + PINMUX_CONSTANTS(117, GPIO_PJ0, J0, RES0, RES1, NOR, USB), + PINMUX_CONSTANTS(118, GPIO_PJ2, J2, RES0, RES1, NOR, SOC_THERM), + PINMUX_CONSTANTS(119, GPIO_PK3, K3, SDMMC2, TRACE, NOR, CCLA), + PINMUX_CONSTANTS(120, GPIO_PK4, K4, SDMMC2, RES1, NOR_AD22, NOR_INT1), + PINMUX_CONSTANTS(121, GPIO_PK2, K2, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(122, GPIO_PI3, I3, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(123, GPIO_PI6, I6, RES0, RES1, NOR, SDMMC2), + PINMUX_CONSTANTS(124, GPIO_PG0, G0, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(125, GPIO_PG1, G1, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(126, GPIO_PG2, G2, RES0, TRACE, NOR, RES3), + PINMUX_CONSTANTS(127, GPIO_PG3, G3, RES0, TRACE, NOR, RES3), + PINMUX_CONSTANTS(128, GPIO_PG4, G4, RES0, TMDS, NOR, SPI4), + PINMUX_CONSTANTS(129, GPIO_PG5, G5, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(130, GPIO_PG6, G6, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(131, GPIO_PG7, G7, RES0, RES1, NOR, SPI4), + PINMUX_CONSTANTS(132, GPIO_PH0, H0, PM3, TRACE, NOR, DTV), + PINMUX_CONSTANTS(133, GPIO_PH1, H1, PM3, TMDS, NOR, DCA), + PINMUX_CONSTANTS(134, GPIO_PH2, H2, PM3, TDMS, NOR, CLDVFS), + PINMUX_CONSTANTS(135, GPIO_PH3, H3, PM3, SPI4, NOR, CLDVFS), + PINMUX_CONSTANTS(136, GPIO_PH4, H4, SDMMC2, RES1, NOR, RES3), + PINMUX_CONSTANTS(137, GPIO_PH5, H5, SDMMC2, RES1, NOR, RES3), + PINMUX_CONSTANTS(138, GPIO_PH6, H6, SDMMC2, TRACE, NOR, DTV), + PINMUX_CONSTANTS(139, GPIO_PH7, H7, SDMMC2, TRACE, NOR, DTV), + PINMUX_CONSTANTS(140, GPIO_PJ7, J7, UD3, RES1, NOR_AD16, NOR_INT2), + PINMUX_CONSTANTS(141, GPIO_PB0, B0, UD3, RES1, NOR, RES3), + PINMUX_CONSTANTS(142, GPIO_PB1, B1, UD3, RES1, NOR, RES3), + PINMUX_CONSTANTS(143, GPIO_PK7, K7, UD3, RES1, NOR, RES3), + PINMUX_CONSTANTS(144, GPIO_PI0, I0, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(145, GPIO_PI1, I1, RES0, RES1, NOR, RES3), + PINMUX_CONSTANTS(146, GPIO_PI2, I2, SDMMC2, TRACE, NOR, RES3), + PINMUX_CONSTANTS(147, GPIO_PI4, I4, SPI4, TRACE, NOR, DCA), + PINMUX_CONSTANTS(148, GEN2_I2C_SCL, T5, I2C2, RES1, NOR, RES3), + PINMUX_CONSTANTS(149, GEN2_I2C_SDA, T6, I2C2, RES1, NOR, RES3), + PINMUX_CONSTANTS(150, SDMMC4_CLK, CC4, SDMMC4, RES1, NOR, RES3), + PINMUX_CONSTANTS(151, SDMMC4_CMD, T7, SDMMC4, RES1, NOR, RES3), + PINMUX_CONSTANTS(152, SDMMC4_DAT0, AA0, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(153, SDMMC4_DAT1, AA1, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(154, SDMMC4_DAT2, AA2, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(155, SDMMC4_DAT3, AA3, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(156, SDMMC4_DAT4, AA4, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(157, SDMMC4_DAT5, AA5, SDMMC4, SPI3, RES2, RES3), + PINMUX_CONSTANTS(158, SDMMC4_DAT6, AA6, SDMMC4, SPI3, NOR, RES3), + PINMUX_CONSTANTS(159, SDMMC4_DAT7, AA7, SDMMC4, RES1, NOR, RES3), + PINMUX_CONSTANTS(161, CAM_MCLK, CC0, VIMCLK_PRI, VIMCLK_ALT1, + VIMCLK_ALT3, SDMMC2), + PINMUX_CONSTANTS(162, GPIO_PCC1, CC1, I2S4, RES1, RES2, SDMMC2), + PINMUX_CONSTANTS(163, GPIO_PBB0, BB0, VGP6, VIMCLK2_PRI, SDMMC2, + VIMCLK2_ALT3), + PINMUX_CONSTANTS(164, CAM_I2C_SCL, BB1, VGP1, I2C3, RES2, SDMMC2), + PINMUX_CONSTANTS(165, CAM_I2C_SDA, BB2, VGP2, I2C3, RES2, SDMMC2), + PINMUX_CONSTANTS(166, GPIO_PBB3, BB3, VGP3, DCA, DCB, SDMMC2), + PINMUX_CONSTANTS(167, GPIO_PBB4, BB4, VGP4, DCA, DCB, SDMMC2), + PINMUX_CONSTANTS(168, GPIO_PBB5, BB5, VGP5, DCA, RES2, SDMMC2), + PINMUX_CONSTANTS(169, GPIO_PBB6, BB6, I2S4, RES1, DCB, SDMMC2), + PINMUX_CONSTANTS(170, GPIO_PBB7, BB7, I2S4, RES1, RES2, SDMMC2), + PINMUX_CONSTANTS(171, GPIO_PCC2, CC2, I2S4, RES1, SDMMC3, SDMMC2), + PINMUX_CONSTANTS(172, JTAG_RTCK, NONE172, RTCK, RES1, RES2, RES3), + PINMUX_CONSTANTS(173, PWR_I2C_SCL, Z6, I2CPMU, RES1, RES2, RES3), + PINMUX_CONSTANTS(174, PWR_I2C_SDA, Z7, I2CPMU, RES1, RES2, RES3), + PINMUX_CONSTANTS(175, KB_ROW0, R0, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(176, KB_ROW1, R1, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(177, KB_ROW2, R2, RES0, RES1, RES2, RES3), + PINMUX_CONSTANTS(178, KB_ROW3, R3, RES0, DCA, SYS_CLK, DCB), + PINMUX_CONSTANTS(179, KB_ROW4, R4, RES0, DCA, RES2, DCB), + PINMUX_CONSTANTS(180, KB_ROW5, R5, RES0, DCA, RES2, DCB), + PINMUX_CONSTANTS(181, KB_ROW6, R6, RES0, DCA_LSC0, DCA_LSPII, DCB), + PINMUX_CONSTANTS(182, KB_ROW7, R7, RES0, RES1, CLDVFS, UA3), + PINMUX_CONSTANTS(183, KB_ROW8, S0, RES0, RES1, CLDVFS, UA3), + PINMUX_CONSTANTS(184, KB_ROW9, S1, RES0, RES1, RES2, UA3), + PINMUX_CONSTANTS(185, KB_ROW10, S2, RES0, RES1, RES2, UA3), + PINMUX_CONSTANTS(186, KB_ROW11, S3, RES0, RES1, RES2, IR3), + PINMUX_CONSTANTS(187, KB_ROW12, S4, RES0, RES1, RES2, IR3), + PINMUX_CONSTANTS(188, KB_ROW13, S5, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(189, KB_ROW14, S6, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(190, KB_ROW15, S7, RES0, SOC_THERM, RES2, RES3), + PINMUX_CONSTANTS(191, KB_COL0, Q0, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(192, KB_COL1, Q1, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(193, KB_COL2, Q2, RES0, RES1, SPI2, RES3), + PINMUX_CONSTANTS(194, KB_COL3, Q3, RES0, DCA, PM3, UA3), + PINMUX_CONSTANTS(195, KB_COL4, Q4, RES0, OWR, SDMMC3, UA3), + PINMUX_CONSTANTS(196, KB_COL5, Q5, RES0, RES1, SDMMC3, RES3), + PINMUX_CONSTANTS(197, KB_COL6, Q6, RES0, RES1, SPI2, UD3), + PINMUX_CONSTANTS(198, KB_COL7, Q7, RES0, RES1, SPI2, UD3), + PINMUX_CONSTANTS(199, CLK_32K_OUT, A0, BLINK, SOC_THERM, RES2, RES3), + PINMUX_CONSTANTS(201, CORE_PWR_REQ, NONE201, PWRON, RES1, RES2, RES3), + PINMUX_CONSTANTS(202, CPU_PWR_REQ, NONE202, CPU, RES1, RES2, RES3), + PINMUX_CONSTANTS(203, PWR_INT_N, NONE203, PMICINTR, RES1, RES2, RES3), + PINMUX_CONSTANTS(204, CLK_32K_IN, NONE204, CLK_32K_IN, RES1, RES2, + RES3), + PINMUX_CONSTANTS(205, OWR, NONE205, OWR, RES1, RES2, RES3), + PINMUX_CONSTANTS(206, DAP1_FS, N0, I2S0, DAP1, NOR, RES3), + PINMUX_CONSTANTS(207, DAP1_DIN, N1, I2S0, DAP1, NOR, RES3), + PINMUX_CONSTANTS(208, DAP1_DOUT, N2, I2S0, DAP1, NOR, SATA), + PINMUX_CONSTANTS(209, DAP1_SCLK, N3, I2S0, DAP1, NOR, RES3), + PINMUX_CONSTANTS(210, DAP_MCLK1_REQ, EE2, DAP, DAP1, SATA, RES3), + PINMUX_CONSTANTS(211, DAP_MCLK1, W4, EXTPERHIP1, DAP2, RES2, RES3), + PINMUX_CONSTANTS(212, SPDIF_IN, K6, SPDIF, RES1, RES2, I2C3), + PINMUX_CONSTANTS(213, SPDIF_OUT, K5, SPDIF, RES1, RES2, I2C3), + PINMUX_CONSTANTS(214, DAP2_FS, A2, I2S1, DAP2, NOR, RES3), + PINMUX_CONSTANTS(215, DAP2_DIN, A4, I2S1, DAP2, NOR, RES3), + PINMUX_CONSTANTS(216, DAP2_DOUT, A5, I2S1, DAP2, NOR, RES3), + PINMUX_CONSTANTS(217, DAP2_SCLK, A3, I2S1, SAP2, NOR, RES3), + PINMUX_CONSTANTS(218, DVFS_PWM, X0, SPI6, CLDVFS, NOR, RES3), + PINMUX_CONSTANTS(219, GPIO_X1_AUD, X1, SPI6, RES1, NOR, RES3), + PINMUX_CONSTANTS(220, GPIO_X3_AUD, X3, SPI6, SPI1, NOR, RES3), + PINMUX_CONSTANTS(221, DVFS_CLK, X2, SPI6, CLDVFS_CLK, NOR, RES3), + PINMUX_CONSTANTS(222, GPIO_X4_AUD, X4, NOR, SPI1, SPI2, DAP2), + PINMUX_CONSTANTS(223, GPIO_X5_AUD, X5, NOR, SPI1, SPI2, RES3), + PINMUX_CONSTANTS(224, GPIO_X6_AUD, X6, SPI6, SPI1, SPI2, NOR), + PINMUX_CONSTANTS(225, GPIO_X7_AUD, X7, RES0, SPI1, SPI2, RES3), + PINMUX_CONSTANTS(228, SDMMC3_CLK, A6, SDMMC3, RES1, RES2, SPI3), + PINMUX_CONSTANTS(229, SDMMC3_CMD, A7, SDMMC3, PM3, UA3, SPI3), + PINMUX_CONSTANTS(230, SDMMC3_DAT0, B7, SDMMC3, RES1, RES2, SPI3), + PINMUX_CONSTANTS(231, SDMMC3_DAT1, B6, SDMMC3, PM3, UA3, SPI3), + PINMUX_CONSTANTS(232, SDMMC3_DAT2, B5, SDMMC3, PM3, DCA, SPI3), + PINMUX_CONSTANTS(233, SDMMC3_DAT3, B4, SDMMC3, PM3, DCB, SPI3), + PINMUX_CONSTANTS(239, PEX_L0_RST_N, DD1, PE0, RES1, RES2, RES3), + PINMUX_CONSTANTS(240, PEX_L0_CLKREQ_N, DD2, PE0, RES1, RES2, RES3), + PINMUX_CONSTANTS(241, PEX_WAKE_N, DD3, PE, RES1, RES2, RES3), + PINMUX_CONSTANTS(243, PEX_L1_RST_N, DD5, PE1, RES1, RES2, RES3), + PINMUX_CONSTANTS(244, PEX_L1_CLKREQ_N, DD6, PE1, RES1, RES2, RES3), + PINMUX_CONSTANTS(248, HDMI_CEC, EE3, CEC, RES1, RES2, RES3), + PINMUX_CONSTANTS(249, SDMMC1_WP_N, V3, SDMMC1, CLK12M, SPI4, UA3), + PINMUX_CONSTANTS(250, SDMMC3_CD_N, V2, SDMMC3, OWR, RES2, RES3), + PINMUX_CONSTANTS(251, GPIO_W2_AUD, W2, SPI6, RES1, SPI2, I2C1), + PINMUX_CONSTANTS(252, GPIO_W3_AUD, W3, SPI6, SPI1, SPI2, I2C1), + PINMUX_CONSTANTS(253, USB_VBUS_EN0, N4, USB, RES1, RES2, RES3), + PINMUX_CONSTANTS(254, USB_VBUS_EN1, N5, USB, RES1, RES2, RES3), + PINMUX_CONSTANTS(255, SDMMC3_CLK_LB_IN, EE5, SDMMC3, RES1, RES2, RES3), + PINMUX_CONSTANTS(256, SDMMC3_CLK_LB_OUT, EE4, SDMMC3, RES1, RES2, RES3), + PINMUX_CONSTANTS(258, RESET_OUT_N, NONE258, RES0, RES1, RES2, RESET), + PINMUX_CONSTANTS(259, KB_ROW16, T0, RES0, RES1, RES2, UC3), + PINMUX_CONSTANTS(260, KB_ROW17, T1, RES0, RES1, RES2, UC3), + PINMUX_CONSTANTS(261, USB_VBUS_EN2, FF1, USB, RES1, RES2, RES3), + PINMUX_CONSTANTS(262, GPIO_PFF2, FF2, SATA, RES1, RES2, RES3), + PINMUX_CONSTANTS(268, DP_HPD, FF0, DP, RES1, RES2, RES3), + + // Where do these go? + /* + PINMUX_JTAG_TRST_N_JTAG_TRST_N = 0, + + PINMUX_JTAG_TDO_JTAG_TDO = 0, + + PINMUX_JTAG_TMS_JTAG_TMS = 0, + + PINMUX_JTAG_TCK_JTAG_TCK = 0, + // What do functions 1 and 2 do? + + PINMUX_JTAG_TDI_JTAG_TDI = 0, + PINMUX_JTAG_TDI_PWR_BREAK = 1, + + PINMUX_TEST_MODE_EN_TEST_MODE_EN = 0, + PINMUX_TEST_MODE_EN_VIMCLK_PRI = 1, + PINMUX_TEST_MODE_EN_VIMCLK_ALT1 = 2, + PINMUX_TEST_MODE_EN_VIMCLK_ALT3 = 3, + + PINMUX_DP_AUX_CH0_P_I2C_CLK = 0, + PINMUX_DP_AUX_CH0_P_SDMMC3_DAT3 = 1, + PINMUX_DP_AUX_CH0_P_PM3_PWM0 = 2, + PINMUX_DP_AUX_CH0_P_DCB_LPM0 = 3, + + PINMUX_DP_AUX_CH0_N_I2C6_DAT = 0, + PINMUX_DP_AUX_CH0_N_SDMMC3_DAT2 = 1, + PINMUX_DP_AUX_CH0_N_PM3_PWM1 = 2, + PINMUX_DP_AUX_CH0_N_DCA_LPM0 = 3, + */ +}; + +#endif /* __SOC_NVIDIA_TEGRA124_PINMUX_H__ */
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Isaac Christensen