[S] Change in coreboot[main]: util/superiotool: Add extra selectors support

[Maxim (Code Review)]

Attention is currently required from: Angel Pons, Felix Held, Paul Menzel.

Hello Angel Pons, Felix Held, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83196?usp=email

to look at the new patch set (#6).

Change subject: util/superiotool: Add extra selectors support
......................................................................

util/superiotool: Add extra selectors support

Some chips have specific selectors (in addition to LDN-register) that
affect the register space. At the same time, the utility doesn't provide
a simple and convenient method for configuring such selectors (as in the
case of LDN-selector) to create a dump, because this may be configured
by several fields of the register, and the values of its other fields
should not change after setting in the BIOS (fintek [1,2]).

Just add a structure with an index, mask, and value for the selector
inside the superio_registers chip for the corresponding LDN to switch
the register bank:

{FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", {

* * *
{NOLDN, "Global",
  {0x28,0x2a,0x2b,0x2c,EOT},
  {0x00,0x00,0x00,0x00,EOT},
  {.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */
},
{0x03, "LPT",
  {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
  {NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */
},

* * *

Tested with Fintek F81966 on Asrock IMB-1222:

- run superiotool on Ubuntu and dump the registers for the board with
  the vendor's firmware;
- add the superio chip initialization code to the board configuration
  in coreboot and build the project;
- boot Ubuntu on the board with coreboot and re-dump the registers;
- the register values from the board configuration code are the same
  in both dumps.

Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e
(Global) -- ESEL[27h] 0x00 (Port Select Register) --
idx 02 07 20 21 23 24 25 26  27 28 29 2a 2b 2c 2d
val 00 0b 15 02 19 34 5a 23  80 a0 f0 45 02 e3 2e
def NA 00 15 02 19 34 00 23  02 a0 00 00 02 0c 28
* * *

The changes do not affect the configuration of existing chips, which
was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D
(the dump before and after the changes are the same).

[1] CB:83004
[2] CB:83019

Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead
Signed-off-by: Maxim Polyakov 
---
M util/superiotool/superiotool.c
M util/superiotool/superiotool.h
2 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83196/6