Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34927 )
Change subject: mainboard/google: Remove uses of #ifndef __PRE_RAM__ ......................................................................
mainboard/google: Remove uses of #ifndef __PRE_RAM__
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/auron/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/slippy/chromeos.c 4 files changed, 4 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34927/1
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 0147a31..c82e37d 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h>
/* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index ecd7592..a5370be 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -15,13 +15,11 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -41,7 +39,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 7880154..859fb0b 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -14,15 +14,13 @@ */
#include <bootmode.h> +#include <boot/coreboot_tables.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index f52bace..772b5a8 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -14,13 +14,11 @@ */
#include <bootmode.h> +#include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -31,7 +29,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) {
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34927
to look at the new patch set (#2).
Change subject: mainboard/google: Remove use of __PRE_RAM__ ......................................................................
mainboard/google: Remove use of __PRE_RAM__
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/auron/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/intel/wtm2/chromeos.c 5 files changed, 5 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34927/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34927 )
Change subject: mainboard/google: Remove use of __PRE_RAM__ ......................................................................
Patch Set 2: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34927 )
Change subject: mainboard/google: Remove use of __PRE_RAM__ ......................................................................
mainboard/google: Remove use of __PRE_RAM__
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34927 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/auron/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/intel/wtm2/chromeos.c 5 files changed, 5 insertions(+), 20 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 0147a31..c82e37d 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -13,15 +13,13 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h>
/* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index ecd7592..a5370be 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -15,13 +15,11 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -41,7 +39,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 7880154..859fb0b 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -14,15 +14,13 @@ */
#include <bootmode.h> +#include <boot/coreboot_tables.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index f52bace..772b5a8 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -14,13 +14,11 @@ */
#include <bootmode.h> +#include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -31,7 +29,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 8022214..556677a 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -14,6 +14,7 @@ */
#include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <soc/gpio.h> @@ -22,9 +23,6 @@ /* Compile-time settings for recovery mode. */ #define REC_MODE_SETTING 0
-#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_recovery_mode_switch(void) {
-
Furquan Shaikh (Code Review) -
Kyösti Mälkki (Code Review)