[XS] Change in coreboot[main]: soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR en...

[Krishna P Bhat D (Code Review)]

Attention is currently required from: Anil Kumar K, Rizwan Qureshi, Subrata Banik.

Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78055?usp=email )

Change subject: soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabled
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Patch Set 4:

(1 comment)

File src/soc/intel/common/block/cse/Kconfig:

https://review.coreboot.org/c/coreboot/+/78055/comment/e70dcdea_15333370 :
PS3, Line 149: 	 Select this config if Platform Service Record(PSR) is supported by the platform. This
             : 	 config is applicable only for Lite SKU, where PSR data backup is required prior to a
             : 	 CSE firmware downgrade during which CSE data is cleared. CSE Lite firmware sync will be
             : 	 performed in ramstage to support PSR data back-up when this config is selected.
> what is the reason behind attaching "CSE Sync in Ramstage" with PSR is the missing part in this help […]

Acknowledged