New patch to review for coreboot: c6a4d47 NOTFORMERGE: fixups for 7172

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7174

-gerrit

commit c6a4d47efa71029eb1e64995c0ffdc70e24d52a4
Author: Edward O'Callaghan 
Date:   Thu Oct 23 18:18:06 2014 +1100

NOTFORMERGE: fixups for 7172

Change-Id: I5284081f6cbab8d85dd88cac8295c58e05230895
    Signed-off-by: Edward O'Callaghan 
---
 src/southbridge/intel/bd82x6x/chip.h | 1 +
 src/southbridge/intel/bd82x6x/sata.c | 7 +++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 0f2f0e9..e8d1da9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {

/* IDE configuration */
    uint8_t sata_port_map;
+	uint8_t sata_port_split;
    uint32_t sata_port0_gen3_tx;
    uint32_t sata_port1_gen3_tx;

diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 65931e1..398a3cc 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -89,8 +89,11 @@ static void sata_init(struct device *dev)
    	reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
    	pci_write_config32(dev, IDE_CONFIG, reg32);

-		/* Set AHCI mode with max 6 ports on first controller */
-		reg16 = 0x0050;
+		/* Set AHCI mode port split flag;
+		 * Switch between max 6/0 or 2/4 ports on first/second controller
+		 * respectively. XXX - correct value for 2/4 split??
+		 */
+		reg16 = config->sata_port_split ? 0x0050 : 0x0050;
    	pci_write_config16(dev, 0x90, reg16);

/* for AHCI, Port Enable is managed in memory mapped space */