Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81550?usp=email )
Change subject: mb/dell/optiplex_9020: Fix SATA port maps ......................................................................
mb/dell/optiplex_9020: Fix SATA port maps
Previously incorrect sets of SATA ports were enabled.
There are no publically available schematics, but I am almost certain the new values are correct.
The original 0x33 value was carlessly copy pasted, and only enables ports 0, 1, 4, 5, leaving 2, 3 disabled.
On the SFF, with 0x33 only the first 2 ports worked. I have verified by plugging in devices under the stock firmware that 0, 1, 2 are the ones that should be enabled, so setting the value to 0x7 per datasheet. This was also tested in practice to work.
I don't have an MT, but I was told the two white ports didn't work with 0x33, so those are most certainly ports 3, 4, hence me setting the value to 0xf. If the MT's working ports are port 0, 1 on the PCH this is correct.
Signed-off-by: Mate Kukri kukri.mate@gmail.com Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81550 Reviewed-by: Paul Menzel paulepanter@mailbox.org Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Eric Lai ericllai@google.com --- M src/mainboard/dell/optiplex_9020/devicetree.cb M src/mainboard/dell/optiplex_9020/overridetree_mt.cb 2 files changed, 3 insertions(+), 1 deletion(-)
Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb index c0b17a1..dce5869 100644 --- a/src/mainboard/dell/optiplex_9020/devicetree.cb +++ b/src/mainboard/dell/optiplex_9020/devicetree.cb @@ -23,7 +23,7 @@ register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" register "gen4_dec" = "0x001c0901" - register "sata_port_map" = "0x33" + register "sata_port_map" = "0x7"
device pci 14.0 on end # xHCI controller device pci 16.0 on end # Management Engine interface 1 diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb index 90205c2..a781960 100644 --- a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb +++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb @@ -3,6 +3,8 @@ chip northbridge/intel/haswell device domain 0 on chip southbridge/intel/lynxpoint + register "sata_port_map" = "0xf" + device pci 1c.1 on end # PCI (via XIO2001 bridge) device pci 1c.2 on end # PCIe 1x slot end