Change in coreboot[master]: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

Add MMIO offsets for USB2 and USB3 port status registers; implement
soc_get_xhci_usb_info() to return the info for elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak 
---
A src/soc/intel/alderlake/xhci.c
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/1

diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c
new file mode 100644
index 0000000..ab2a48c
--- /dev/null
+++ b/src/soc/intel/alderlake/xhci.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/xhci.h>
+
+/*
+ * Information obtained from Intel doc# 630094, ADL-P PCH EDS Vol. 2,
+ * as well as doc# 626817, ADL-P PCH EDS Vol. 1
+ */
+
+#define XHCI_USB2_PORT_STATUS_REG	0x480
+#define XHCI_USB3_PORT_STATUS_REG	0x540
+#define XHCI_USB2_PORT_NUM		10
+#define XHCI_USB3_PORT_NUM		4
+
+static const struct xhci_usb_info usb_info = {
+	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
+
+const struct xhci_usb_info *soc_get_xhci_usb_info(void)
+{
+	return &usb_info;
+}

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47397/1/src/soc/intel/alderlake/xhc... 
File src/soc/intel/alderlake/xhci.c:

PS1: 
File needs to be added to Makefile?

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47397/1/src/soc/intel/alderlake/xhc... 
File src/soc/intel/alderlake/xhci.c:

PS1:
> File needs to be added to Makefile?

I added it in CB:47399, when the soc_... function is first compiled in. I can add it here though, I suppose the linker will remove it until it's needed.

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47397

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

Add MMIO offsets for USB2 and USB3 port status registers; implement
soc_get_xhci_usb_info() to return the info for elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/xhci.c
2 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/2

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Caveh Jalali, Nick Vaccaro, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47397

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

Add MMIO offsets for USB2 and USB3 port status registers; implement
soc_get_xhci_usb_info() to return the info for elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/xhci.c
2 files changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/3

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Caveh Jalali, Nick Vaccaro, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47397

to look at the new patch set (#4).

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

Add MMIO offsets for USB2 and USB3 port status registers; implement
soc_get_xhci_usb_info() to return the info for elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/xhci.c
2 files changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/4

[Tim Wawrzynczak (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Caveh Jalali, Nick Vaccaro, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47397

to look at the new patch set (#5).

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/xhci.c
2 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/5

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47397/1/src/soc/intel/alderlake/xhc... 
File src/soc/intel/alderlake/xhci.c:

PS1:
> I added it in CB:47399, when the soc_... function is first compiled in. […]

Done

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 5: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/47397/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47397/1//COMMIT_MSG@11 
PS1, Line 11: 
BUG and TEST fields missing.

[Patrick Georgi (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/47397/comment/ee4ba524_63f08efb 
PS1, Line 11:
> BUG and TEST fields missing.

While a nice thing to have, they're not required here.

[Nick Vaccaro (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 5: Code-Review+2

[Furquan Shaikh (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

Patch Set 5: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47397 )

Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
......................................................................

soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support

Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) 
Reviewed-by: Nick Vaccaro 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/xhci.c
2 files changed, 45 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Nick Vaccaro: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index f31cf98..fc3d63e 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -45,6 +45,7 @@
 ramstage-y += smmrelocate.c
 ramstage-y += soundwire.c
 ramstage-y += systemagent.c
+ramstage-y += xhci.c

smm-y += gpio.c
 smm-y += p2sb.c
diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c
new file mode 100644
index 0000000..9226336
--- /dev/null
+++ b/src/soc/intel/alderlake/xhci.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_type.h>
+#include <intelblocks/xhci.h>
+#include <soc/pci_devs.h>
+
+/*
+ * Information obtained from Intel doc# 630094, ADL-P PCH EDS Vol. 2,
+ * as well as doc# 626817, ADL-P PCH EDS Vol. 1
+ */
+
+#define PCH_XHCI_USB2_PORT_STATUS_REG	0x480
+#define PCH_XHCI_USB3_PORT_STATUS_REG	0x540
+#define PCH_XHCI_USB2_PORT_NUM		10
+#define PCH_XHCI_USB3_PORT_NUM		4
+
+#define TCSS_XHCI_USB2_PORT_STATUS_REG	0x480
+#define TCSS_XHCI_USB3_PORT_STATUS_REG	0x540
+#define TCSS_XHCI_USB2_PORT_NUM		10
+#define TCSS_XHCI_USB3_PORT_NUM		4
+
+static const struct xhci_usb_info usb_info = {
+	.usb2_port_status_reg = PCH_XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = PCH_XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = PCH_XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = PCH_XHCI_USB3_PORT_NUM,
+};
+
+static const struct xhci_usb_info tcss_usb_info = {
+	.usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM,
+};
+
+const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
+{
+	if (xhci_dev == PCH_DEVFN_XHCI)
+		return &usb_info;
+	else if (xhci_dev == SA_DEVFN_TCSS_XHCI)
+		return &tcss_usb_info;
+
+	return NULL;
+}