Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Subrata Banik (Code Review)]

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 17:

(1 comment)

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/73449e90_acd69e82 
PS17, Line 212: 	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> Here are the actual values used by/expected by JSL FSP: […]

I agree with Tim, we just need to ack here , this is a FSP bug in documenting things and this code just W/A it to make it proper. may be in the code comment and in commit msg as well ?