Change in ...coreboot[master]: mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30015 )
Change subject: mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters ......................................................................
mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
This implementation configures below parameters:
1. Enable SaGv, isclk. 2. Set Pcie rootport enable, Clock source usage and clkreq. 3. Configure SATA and LPSS controllers parameters. 4. Enable CNVI controller, configure Wifi end device under PCIE RP1. 5. Add TPM device support under GSPI1.
Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/c/30015 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/soc/intel/icelake/chip.h 3 files changed, 279 insertions(+), 64 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index a971332..0d2ea76 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -4,28 +4,40 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1"
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB2 Bluetooth + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -36,6 +48,8 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1"
+ register "PrmrrSize" = "0x10000000" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" @@ -53,12 +67,22 @@ register "PcieRpEnable[14]" = "1" register "PcieRpEnable[15]" = "1"
- register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[0]" = "2" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" + register "PcieClkSrcUsage[5]" = "0xE" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80"
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -66,6 +90,69 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }"
# Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -74,29 +161,32 @@ register "sdcard_cd_gpio" = "GPP_G5"
# Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0"
# Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | #+-------------------+---------------------------+ + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, }, }"
device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -188,6 +278,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi @@ -203,7 +294,7 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 + device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -211,12 +302,17 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 @@ -232,12 +328,15 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end end - end # LPC Interface + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 787097e..62c7a82 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -4,28 +4,40 @@ device lapic 0 on end end
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1"
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB3/2 Type A port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Bluetooth + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-C Port3 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # UNUSED - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # UNUSED - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # USB2 Type A port1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3 WLAN - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # UNUSED + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" @@ -35,8 +47,8 @@
register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + + register "PrmrrSize" = "0x10000000"
register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -52,13 +64,25 @@ register "PcieRpEnable[11]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1"
- register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "0x80" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "2" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80"
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -66,6 +90,69 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }"
# Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -74,13 +161,32 @@ register "sdcard_cd_gpio" = "GPP_G5"
# Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + }"
device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -172,6 +278,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM chip drivers/intel/wifi register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi @@ -187,20 +294,25 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA + device pci 17.0 on end # SATA device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 @@ -216,12 +328,15 @@ device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end end - end # LPC Interface + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index c8653b2..3e2b78a 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -115,6 +115,7 @@ uint16_t usb3_wake_enable_bitmap;
/* SATA related */ + uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8];
-
Subrata Banik (Code Review)