[XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL - coreboot-gerrit

3 Sep 2024


      Attention is currently required from: Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84178?usp=email )
Change subject: soc/intel/common/block: Include register offsets for POWER_CTL
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Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84178/comment/a348e7f1_7b0e1b52?usp... :
PS2, Line 7: src/soc/intel/cmn/block/inc:
...
soc/intel/common/block: Include register offsets for `POWER_CTL`
Acknowledged
https://review.coreboot.org/c/coreboot/+/84178/comment/d3d121d6_87575245?usp... :
PS2, Line 10: 1fc
...
0x1fc
Acknowledged
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Gerrit-MessageType: comment
Gerrit-Project: coreboot
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Gerrit-Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Gerrit-Change-Number: 84178
Gerrit-PatchSet: 2
Gerrit-Owner: Saurabh Mishra mishra.saurabh@intel.com
Gerrit-Reviewer: Subrata Banik subratabanik@google.com
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