Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46908 )
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 9 files changed, 26 insertions(+), 123 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46908/1
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 6dd8559..f44d304 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,18 @@
#include <southbridge/intel/lynxpoint/pch.h>
+static int cstate_set_lp[3] = { + 2, + 3, + 9, +}; + +static int cstate_set_trad[3] = { + 1, + 3, + 5, +}; + static int get_cores_per_package(void) { struct cpuinfo_x86 c; @@ -30,41 +42,6 @@ return cores; }
-static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -119,18 +96,12 @@
static void generate_C_state_entries(void) { + acpi_cstate_t map[3]; + int *set; + int i; + struct cpu_info *info; struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return;
/* Find CPU map of supported C-states */ info = cpu_info(); @@ -140,25 +111,18 @@ if (!cpu || !cpu->cstates) return;
- acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ + if (haswell_is_ult()) + set = cstate_set_lp; + else + set = cstate_set_trad;
- /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); + for (i = 0; i < ARRAY_SIZE(map); i++) { + map[i] = cpu->cstates[set[i]]; + map[i].ctype = i + 1; + }
- /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); }
static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 7d41461..9db1ad3 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -4,15 +4,5 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC
struct cpu_intel_haswell_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ - int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index d257f18..e7dfa74 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,13 +5,6 @@
device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 8f36896..cf73e39 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -5,13 +5,6 @@
device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8fdfbd7..f9a56d7 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -18,14 +18,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 200721b..043ead6 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -23,14 +23,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index ad3d35a..6d2342e 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -16,14 +16,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" - - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" end end
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 8c35681..33ff903 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -13,12 +13,6 @@ register "ec_present" = "true" device cpu_cluster 0x0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index ffcc56d..3a0dfbe 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -4,13 +4,6 @@
device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end
Hello build bot (Jenkins), Tristan Corrick, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46908
to look at the new patch set (#5).
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 9 files changed, 26 insertions(+), 123 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46908/5
Hello build bot (Jenkins), Tristan Corrick, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46908
to look at the new patch set (#7).
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 10 files changed, 26 insertions(+), 131 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46908/7
Hello build bot (Jenkins), Tristan Corrick, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46908
to look at the new patch set (#13).
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 10 files changed, 26 insertions(+), 129 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46908/13
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46908 )
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
Patch Set 14: Code-Review+1
(1 comment)
File src/cpu/intel/haswell/acpi.c:
https://review.coreboot.org/c/coreboot/+/46908/comment/bf4bbca3_c82914f5 PS14, Line 16: : static int cstate_set_lp[3] = { : 2, : 3, : 9, : }; : : static int cstate_set_trad[3] = { : 1, : 3, : 5, : }; If those match with the enum values in haswell_init.c it would be nice to reuse those.
Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46908 )
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
Patch Set 14:
(1 comment)
File src/cpu/intel/haswell/acpi.c:
https://review.coreboot.org/c/coreboot/+/46908/comment/fd3087ba_753583e8 PS14, Line 16: : static int cstate_set_lp[3] = { : 2, : 3, : 9, : }; : : static int cstate_set_trad[3] = { : 1, : 3, : 5, : };
If those match with the enum values in haswell_init.c it would be nice to reuse those.
Done in the next change: CB:46923
This patch simply factors out the numbers. I didn't want to replace them with enum values in the same commit, as it would be harder to follow what is going on.
Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46908 )
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
Patch Set 14: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46908 )
Change subject: cpu/intel/haswell: Factor out ACPI C-state values ......................................................................
cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 10 files changed, 26 insertions(+), 129 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index b757dc6..d257d86 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,18 @@
#include <southbridge/intel/lynxpoint/pch.h>
+static int cstate_set_lp[3] = { + 2, + 3, + 9, +}; + +static int cstate_set_trad[3] = { + 1, + 3, + 5, +}; + static int get_cores_per_package(void) { struct cpuinfo_x86 c; @@ -30,41 +42,6 @@ return cores; }
-static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -119,18 +96,12 @@
static void generate_C_state_entries(void) { + acpi_cstate_t map[3]; + int *set; + int i; + struct cpu_info *info; struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return;
/* Find CPU map of supported C-states */ info = cpu_info(); @@ -140,25 +111,18 @@ if (!cpu || !cpu->cstates) return;
- acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ + if (haswell_is_ult()) + set = cstate_set_lp; + else + set = cstate_set_trad;
- /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); + for (i = 0; i < ARRAY_SIZE(map); i++) { + map[i] = cpu->cstates[set[i]]; + map[i].ctype = i + 1; + }
- /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); }
static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 7c2df10..16f1079 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -31,14 +31,6 @@ };
struct cpu_intel_haswell_config { - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ - int tcc_offset; /* TCC Activation Offset */
struct cpu_vr_config vr_config; diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 024d1f0..43a65f8 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,13 +5,6 @@
device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 45119f9..7b08af9 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -5,13 +5,6 @@
device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 176fced..8c54f6a 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -18,14 +18,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 99cae7a..d989545 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -20,14 +20,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 712d75e..a56a48b 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -15,14 +15,6 @@ register "usb_xhci_on_resume" = "true" device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_battery" = "2" - register "c2_battery" = "3" - register "c3_battery" = "9" - - register "c1_acpower" = "2" - register "c2_acpower" = "3" - register "c3_acpower" = "9" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 797230c..37cff88 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -16,14 +16,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" - - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" end end
diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index fb0442d..8db28cb 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -15,12 +15,6 @@ register "ec_present" = "true" device cpu_cluster 0x0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 6d64a90..6cd3ab7 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -4,13 +4,6 @@
device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Patrick Georgi (Code Review)