Change in coreboot[master]: soc/intel/jsl: Add CdClock config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Kane Chen, Patrick Rudolph.
Hello build bot (Jenkins), Jamie Chen, Kane Chen, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60009

to look at the new patch set (#8).

Change subject: soc/intel/jsl: Add CdClock config
......................................................................

soc/intel/jsl: Add CdClock config

This dev tree config controls the CdClock for Jasperlake.

BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang 
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
3 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/60009/8