Change in coreboot[master]: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44530 )
Change subject: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3 ......................................................................
mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3
There are only headers for the SoC's UART 0 and 1 on the board.
BUG=b:165020060 TEST=Linux only detects UART 0 and 1.
Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44530/1
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index ffc18a0..0004ecd 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -155,4 +155,10 @@ device pci 18.6 on end device pci 18.7 on end end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + end # chip soc/amd/picasso
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44530 )
Change subject: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3 ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44530 )
Change subject: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3 ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44530 )
Change subject: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3 ......................................................................
mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3
There are only headers for the SoC's UART 0 and 1 on the board.
BUG=b:165020060 TEST=Linux only detects UART 0 and 1.
Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index ffc18a0..0004ecd 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -155,4 +155,10 @@ device pci 18.6 on end device pci 18.7 on end end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + end # chip soc/amd/picasso
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Raul Rangel (Code Review)