Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61431
to look at the new patch set (#3).
Change subject: soc/intel/common/cse: Rework `heci_disable` function ......................................................................
soc/intel/common/cse: Rework `heci_disable` function
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure.
BUG=none TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 --- M src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 7 files changed, 71 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/3