[S] Change in coreboot[main]: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER

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[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84200?usp=email )

Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
......................................................................

soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER

Systemagent assumes GSM region is next to TSEG region, but some SoC may
not have GSM region (https://review.coreboot.org/c/coreboot/+/84108).
On such platforms, TSEG region is limited by the TSEG limit register,
and the default offset for that is (TSEG + 4).

Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af
Signed-off-by: Yuchi Chen 
---
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_early.c
2 files changed, 14 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84200/1

diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
index 42d579a..1fbc861 100644
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -55,4 +55,10 @@
    help
      Specify if the SOC has BDSM and BGSM registres.

+config HAVE_TSEG_LIMIT_REGISTER
+	bool
+	default n
+	help
+	  Specify if SoC has TSEG limit register next to TSEG register.
+
 endif
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index aecdfbb..9a03f19 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -148,7 +148,14 @@

size_t sa_get_tseg_size(void)
 {
-	return sa_get_gsm_base() - sa_get_tseg_base();
+	if (!CONFIG(HAVE_TSEG_LIMIT_REGISTER)) {
+		return sa_get_gsm_base() - sa_get_tseg_base();
+	} else {
+		/* TSEG limit is next to TSEG by default. */
+		return soc_systemagent_fixup_address(TSEG + 4,
+						     pci_read_config32(SA_DEV_ROOT, TSEG + 4)) -
+		       sa_get_tseg_base();
+	}
 }

union dpr_register txt_get_chipset_dpr(void)