[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 86:

(5 comments)

Patchset:

PS81:
> @[e-mail], can you please ensure you are following CB:84182 and CB:84183 while creating ramstage CL for panther lake?

Also, CB:84217 and CB:84220

File src/soc/intel/pantherlake/chipset.cb:

https://review.coreboot.org/c/coreboot/+/83798/comment/c03367eb_2ee1fec7?usp... :
PS50, Line 15:
> I am checking this data from PNP team.

ping, if this is good time to check this ?

File src/soc/intel/pantherlake/elog.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/ef4164a5_6a1c68bf?usp... :
PS71, Line 140:
> Yes. The code is ready once GPE1 changes CLs are merged, I will work with […]

Acknowledged

File src/soc/intel/pantherlake/pmutil.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/11f79fe1_a5fd4f20?usp... :
PS71, Line 110:
> Yes. The code is ready once GPE1 changes CLs are merged, I will work with […]

Acknowledged

File src/soc/intel/pantherlake/retimer.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/aa49213d_260e592a?usp... :
PS71, Line 19: 
             : 	for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
> Hi, declaring variables of the same type together in for loop is accepted in c.
> Here, variable i is "uint8_t " type, while ec_port variable is declared "int".
> This will give an error since mixing types in the initialization section is not allowed.
>
> Can be used as below?
>   for (int i = 0, ec_port = 0; i < MAX_TYPE_C_PORTS; i++) {

sure