Change in coreboot[master]: mb/google/skyrim: Configure SD card sequence

[Ian Feng (Code Review)]

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63739 )

Change subject: mb/google/skyrim: Configure SD card sequence
......................................................................

mb/google/skyrim: Configure SD card sequence

Add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.

BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)

Signed-off-by: Ian Feng 
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
---
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63739/1

diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c
index 6ff2906..9131329 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c
+++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c
@@ -186,6 +186,8 @@
    /* Power on WLAN */
    /* EN_PP3300_WLAN */
    PAD_GPO(GPIO_9, HIGH),
+	/* SD_AUX_RESET_L  */
+	PAD_GPO(GPIO_27, LOW),
 };

/* PCIE_RST needs to be brought high before FSP-M runs */
@@ -195,6 +197,8 @@
    PAD_GPO(GPIO_7, HIGH),
    /* PCIE_RST0_L */
    PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
+	/* SD_AUX_RESET_L  */
+	PAD_GPO(GPIO_27, HIGH),
 };

__weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)