Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7236
-gerrit
commit 1925424326efaa0a1280d85659b1cd1dc6281a9f Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Wed Oct 29 08:45:33 2014 +1100
northbridge/via/cn400: Greatly clean up code
* Fix 'device_t' usage to be 'struct device *' * Consolidate register dumping debug function * Fix serious typo in pci driver decl
Motivated by: vlink.c:233:39: error: unused variable 'cn400_pm_operations' static const struct device_operations cn400_pm_operations = { ^ Found-by: Clang Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com Change-Id: Ibbace4f7d9ebeb4b1bac688ad2f6abce23fae3cc --- src/northbridge/via/cn400/Makefile.inc | 1 + src/northbridge/via/cn400/agp.c | 47 ++++-------------- src/northbridge/via/cn400/cn400.h | 11 +++-- src/northbridge/via/cn400/cn400_regdump.c | 49 +++++++++++++++++++ src/northbridge/via/cn400/northbridge.c | 33 ++++--------- src/northbridge/via/cn400/northbridge.h | 2 +- src/northbridge/via/cn400/raminit.c | 2 +- src/northbridge/via/cn400/raminit.h | 2 +- src/northbridge/via/cn400/vga.c | 19 +------- src/northbridge/via/cn400/vlink.c | 79 ++----------------------------- 10 files changed, 87 insertions(+), 158 deletions(-)
diff --git a/src/northbridge/via/cn400/Makefile.inc b/src/northbridge/via/cn400/Makefile.inc index 667c71a..ff1da08 100644 --- a/src/northbridge/via/cn400/Makefile.inc +++ b/src/northbridge/via/cn400/Makefile.inc @@ -18,6 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+ramstage-y += cn400_dumpreg.c ramstage-y += northbridge.c ramstage-y += agp.c ramstage-y += vga.c diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c index ce814c5..6c47d96 100644 --- a/src/northbridge/via/cn400/agp.c +++ b/src/northbridge/via/cn400/agp.c @@ -18,21 +18,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <console/console.h> #include <arch/io.h> -#include <stdint.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <console/console.h> +#include <stdint.h> + #include "northbridge.h" #include "cn400.h"
/* This is the main AGP device, and only one used when configured for AGP 2.0 */ -static void agp_init(device_t dev) +static void agp_init(struct device *dev) { u32 reg32; - u8 reg8; - int i, j;
/* Some of this may not be necessary (should be handled by the OS). */ printk(BIOS_DEBUG, "Enabling AGP.\n"); @@ -111,20 +110,7 @@ static void agp_init(device_t dev) pci_write_config8(dev, 0xc0, 0x04); pci_write_config8(dev, 0xc1, 0x02);
-#ifdef DEBUG_CN400 - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif + cn400_dumpreg(dev); }
static const struct device_operations agp_operations = { @@ -141,7 +127,7 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_AGP, };
-static void agp_bridge_read_resources (device_t dev) +static void agp_bridge_read_resources (struct device *dev) { struct resource *res;
@@ -158,17 +144,14 @@ static void agp_bridge_read_resources (device_t dev) res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } + /* * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the * config in this device takes presidence. We configure both just to be safe. */ -static void agp_bridge_init(device_t dev) +static void agp_bridge_init(struct device *dev) { - u8 reg8; - int i, j; - printk(BIOS_DEBUG, "Entering %s\n", __func__);
pci_write_config16(dev, 0x4, 0x0107); @@ -207,19 +190,7 @@ static void agp_bridge_init(device_t dev) pci_write_config8(dev, 0x44, 0x34); pci_write_config8(dev, 0x45, 0x72);
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - + cn400_dumpreg(dev); }
static const struct device_operations agp_bridge_operations = { diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h index 2df30a6..ad61c17 100644 --- a/src/northbridge/via/cn400/cn400.h +++ b/src/northbridge/via/cn400/cn400.h @@ -18,11 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef _CN400_H +#define _CN400_H + #ifndef __PRE_RAM__ // HACK -static inline void cn400_noop(device_t dev) -{ -} +static inline void cn400_noop(device_t dev) {} #endif
#define DEBUG_CN400 @@ -54,3 +55,7 @@ static inline void cn400_noop(device_t dev) #define RAM_COMMAND_MSR_LOW (const char) 0x03 #define RAM_COMMAND_CBR (const char) 0x04 #define RAM_COMMAND_MSR_HIGH (const char) 0x05 + +void cn400_dumpreg(struct device *dev); + +#endif /* _CN400_H */ diff --git a/src/northbridge/via/cn400/cn400_regdump.c b/src/northbridge/via/cn400/cn400_regdump.c new file mode 100644 index 0000000..d4a025d --- /dev/null +++ b/src/northbridge/via/cn400/cn400_regdump.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <console/console.h> +#include <stdint.h> + +#include "cn400.h" + +void cn400_dumpreg(struct device *dev) +{ +#ifdef DEBUG_CN400 + u8 reg8; + int i, j; + + printk(BIOS_SPEW, "CN400 Entering [ %s ]\n", __func__); + + printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); + + for (i = 0 ; i < 16; i++) + { + printk(BIOS_SPEW, "%02X: ", i*16); + for (j = 0; j < 16; j++) + { + reg8 = pci_read_config8(dev, j+(i*16)); + printk(BIOS_SPEW, "%02X ", reg8); + } + printk(BIOS_SPEW, "\n"); + } +#endif +} diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 149eab3..38551f2 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,12 +34,11 @@ #include "northbridge.h" #include "cn400.h"
-static void memctrl_init(device_t dev) +static void memctrl_init(struct device *dev) { - device_t vlink_dev; + struct device *vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; - int i, j;
printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n"); /* vlink mirror */ @@ -109,20 +108,8 @@ static void memctrl_init(device_t dev) reg8 |= 0x01; pci_write_config8(dev, 0xA0, reg8);
-#ifdef DEBUG_CN400 - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); + cn400_dumpreg(dev);
- for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif printk(BIOS_SPEW, "Leaving cn400 %s.\n", __func__); }
@@ -140,7 +127,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, };
-static void cn400_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(struct device *dev) { struct resource *resource;
@@ -162,7 +149,7 @@ static void cn400_domain_read_resources(device_t dev) }
#ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, +static void ram_reservation(struct device *dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +164,9 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif
-static void cn400_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; u32 pci_tolm;
printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +206,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); }
-static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device *dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__);
@@ -236,12 +223,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); }
-static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device *dev) { }
diff --git a/src/northbridge/via/cn400/northbridge.h b/src/northbridge/via/cn400/northbridge.h index 1fa848f..be6a8b1 100644 --- a/src/northbridge/via/cn400/northbridge.h +++ b/src/northbridge/via/cn400/northbridge.h @@ -21,6 +21,6 @@ #ifndef NORTHBRIDGE_VIA_CN400_H #define NORTHBRIDGE_VIA_CN400_H
-extern unsigned int cn400_scan_root_bus(device_t root, unsigned int max); +extern unsigned int cn400_scan_root_bus(struct device *root, unsigned int max);
#endif /* NORTHBRIDGE_VIA_CN400_H */ diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index d15a633..c666418 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -61,7 +61,7 @@ static void print_val(char *str, int val) * * @param dev The northbridge's CPU Host Interface (D0F2). */ -static void c3_cpu_setup(device_t dev) +static void c3_cpu_setup(struct device *dev) { /* Host bus interface registers (D0F2 0x50-0x67) */ /* Taken from CN700 and updated from running CN400 */ diff --git a/src/northbridge/via/cn400/raminit.h b/src/northbridge/via/cn400/raminit.h index 89ea0d6..d35a1d3 100644 --- a/src/northbridge/via/cn400/raminit.h +++ b/src/northbridge/via/cn400/raminit.h @@ -28,4 +28,4 @@ struct mem_controller { u8 channel0[DIMM_SOCKETS]; };
-#endif +#endif /* RAMINIT_H */ diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index a2afdce..daa1bf1 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -76,7 +76,7 @@ static int via_cn400_int15_handler(void) return res; }
-static void vga_init(device_t dev) +static void vga_init(struct device *dev) { u8 reg8;
@@ -120,22 +120,7 @@ static void vga_init(device_t dev) outb(0x39, SR_INDEX); outb(reg8, SR_DATA);
-#ifdef DEBUG_CN400 - int i, j; - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } -#endif + cn400_dumpreg(dev); }
static const struct device_operations vga_operations = { diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c index c98982e..d827712 100644 --- a/src/northbridge/via/cn400/vlink.c +++ b/src/northbridge/via/cn400/vlink.c @@ -32,12 +32,10 @@ static void noop_1k(u32 knops) for (i = 0; i < 1024 * knops; i++) { __asm__ volatile ("nop\n\t"); } - - return; }
/* Vlink Performance Improvements */ -static void vlink_init(device_t dev) +static void vlink_init(struct device *dev) { u8 reg, reg8; int i, j; @@ -135,33 +133,11 @@ static const struct pci_driver vlink_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_VLINK, };
-static void c3_host_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - static const struct device_operations c3_host_operations = { .read_resources = cn400_noop, .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = c3_host_init, + .init = cn400_dumpreg, .ops_pci = 0, };
@@ -171,34 +147,11 @@ static const struct pci_driver c3_host_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_HOST, };
- -static void c3_err_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - static const struct device_operations c3_err_operations = { .read_resources = cn400_noop, .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = c3_err_init, + .init = cn400_dumpreg, .ops_pci = 0, };
@@ -208,38 +161,16 @@ static const struct pci_driver c3_err_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_ERR, };
-static void cn400_pm_init(device_t dev) -{ - u8 reg8; - int i, j; - - printk(BIOS_SPEW, "Entering CN400 %s\n", __func__); - - printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); - - for (i = 0 ; i < 16; i++) - { - printk(BIOS_SPEW, "%02X: ", i*16); - for (j = 0; j < 16; j++) - { - reg8 = pci_read_config8(dev, j+(i*16)); - printk(BIOS_SPEW, "%02X ", reg8); - } - printk(BIOS_SPEW, "\n"); - } - -} - static const struct device_operations cn400_pm_operations = { .read_resources = cn400_noop, .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = cn400_pm_init, + .init = cn400_dumpreg, .ops_pci = 0, };
static const struct pci_driver cn400_pm_driver __pci_driver = { - .ops = &c3_err_operations, + .ops = &cn400_pm_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_PM, };
-
Edward O'Callaghan