Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47623 )
Change subject: [WIP] plot TxDQ aka timC ......................................................................
[WIP] plot TxDQ aka timC
Change-Id: I6204c874ef616a20bffa305ffee4698a5e08bdc2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47623/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4f54016..14f7dad 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1613,6 +1613,17 @@ stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } + + printk(BIOS_ERR, "Channel %d results:\n", channel); + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + for (timC = 0; timC <= MAX_TIMC; timC++) { + printk(BIOS_ERR, "% 5d\t", timC); + FOR_ALL_LANES { + printk(BIOS_ERR, "%c", stats[lane][timC] ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + FOR_ALL_LANES { struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane]));
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47623
to look at the new patch set (#2).
Change subject: [WIP] improve plots for TxDQ ......................................................................
[WIP] improve plots for TxDQ
Change-Id: I6204c874ef616a20bffa305ffee4698a5e08bdc2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47623/2