HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6455
-gerrit
commit 5c89c2eb5a41511da82eecfe1398b306f5530c0d Author: Elyes HAOUAS ehaouas@noos.fr Date: Mon Aug 4 08:22:10 2014 +0200
Add missing header guards
Change-Id: I065297cdb20dc0f31c1eddc03f0382d5c59ec7e7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/amd/amdfam10/amdfam10.h | 6 +++--- src/northbridge/amd/amdfam10/nums.h | 7 +++---- src/northbridge/amd/amdk8/amdk8.h | 7 +++---- src/northbridge/amd/amdmct/amddefs.h | 5 +++++ src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 5 +++++ src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/e7520/e7520.h | 5 +++++ src/northbridge/intel/e7525/e7525.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/via/cn400/cn400.h | 5 +++++ src/northbridge/via/cn700/cn700.h | 5 +++++ src/northbridge/via/cx700/registers.h | 5 +++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 5 +++++ src/southbridge/intel/bd82x6x/nvs.h | 5 +++++ src/southbridge/intel/fsp_bd82x6x/nvs.h | 5 +++++ src/southbridge/intel/fsp_rangeley/nvs.h | 5 +++++ src/southbridge/intel/i82801dx/nvs.h | 5 +++++ src/southbridge/intel/i82801gx/nvs.h | 5 +++++ src/southbridge/intel/i82801ix/nvs.h | 5 +++++ src/southbridge/intel/i82870/82870.h | 5 +++++ src/southbridge/intel/ibexpeak/nvs.h | 5 +++++ src/southbridge/intel/lynxpoint/nvs.h | 5 +++++ src/southbridge/nvidia/ck804/early_setup_ss.h | 5 +++++ src/southbridge/nvidia/ck804/early_smbus.h | 5 +++++ src/southbridge/nvidia/mcp55/early_setup_ss.h | 5 +++++ src/southbridge/ricoh/rl5c476/rl5c476.h | 7 +++++-- src/southbridge/sis/sis966/early_setup_ss.h | 5 +++++ src/southbridge/ti/pci7420/pci7420.h | 5 +++++ src/southbridge/via/common/via_early_smbus.h | 5 +++++ src/southbridge/via/vt8237r/nvs.h | 5 +++++ src/southbridge/via/vt82c686/vt82c686.h | 5 +++++ 34 files changed, 163 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 6e71b4e..da9792f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef AMDFAM10_H +#ifndef NORTHBRIDGE_AMD_AMDFAM10_AMDFAM10_H +#define NORTHBRIDGE_AMD_AMDFAM10_AMDFAM10_H
-#define AMDFAM10_H /* Definitions of various FAM10 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 @@ -1200,4 +1200,4 @@ u8 get_sbbusn(u8 sblk); #include "northbridge/amd/amdht/porting.h" BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
-#endif /* AMDFAM10_H */ +#endif /* NORTHBRIDGE_AMD_AMDFAM10_AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h index 12bac5d..a2856b2 100644 --- a/src/northbridge/amd/amdfam10/nums.h +++ b/src/northbridge/amd/amdfam10/nums.h @@ -17,9 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef AMDFAM10_NUMS_H - -#define AMDFAM10_NUMS_H +#ifndef NORTHBRIDGE_AMD_AMDFAM10_NUMS_H +#define NORTHBRIDGE_AMD_AMDFAM10_NUMS_H
#if CONFIG_MAX_PHYSICAL_CPUS > 8 #if CONFIG_MAX_PHYSICAL_CPUS > 32 @@ -37,4 +36,4 @@ //it could be more bigger #define HC_POSSIBLE_NUM 32
-#endif +#endif /* NORTHBRIDGE_AMD_AMDFAM10_NUMS_H */ diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..2f7ee9c 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -1,6 +1,5 @@ -#ifndef AMDK8_H - -#define AMDK8_H +#ifndef NORTHBRIDGE_AMD_AMDK8_AMDK8_H +#define NORTHBRIDGE_AMD_AMDK8_AMDK8_H
#if CONFIG_K8_REV_F_SUPPORT
@@ -19,4 +18,4 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_
void cpus_ready_for_init(void);
-#endif /* AMDK8_H */ +#endif /* NORTHBRIDGE_AMD_AMDK8_AMDK8_H */ diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9efc1db..2798263 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_AMD_AMDMCT_AMDDEFS_H +#define NORTHBRIDGE_AMD_AMDMCT_AMDDEFS_H + /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */
/* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ @@ -148,3 +151,5 @@ #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 + +#endif /* NORTHBRIDGE_AMD_AMDMCT_AMDDEFS_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index e989ae3..5d487e6 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_AMD_AMDMCT_MCT_MCT_D_GCC_H +#define NORTHBRIDGE_AMD_AMDMCT_MCT_MCT_D_GCC_H
static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { @@ -376,3 +378,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* NORTHBRIDGE_AMD_AMDMCT_MCT_MCT_D_GCC_H */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index abe6e7b..1e4016b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_AMD_AMDMCT_MCT_DDR3_MCT_D_GCC_H +#define NORTHBRIDGE_AMD_AMDMCT_MCT_DDR3_MCT_D_GCC_H + static inline void _WRMSR(u32 addr, u32 lo, u32 hi) { __asm__ volatile ( @@ -358,3 +361,5 @@ static u8 oemNodePresent_D(u8 Node, u8 *ret) *ret = 0; return 0; } + +#endif /* NORTHBRIDGE_AMD_AMDMCT_MCT_DDR3_MCT_D_GCC_H */ diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index 1e431b1..23a135c 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_INTEL_E7501_E7501_H +#define NORTHBRIDGE_INTEL_E7501_E7501_H + /* * e7501.h: PCI configuration space for the Intel E7501 memory controller */ @@ -77,3 +80,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7501_E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 08b681a..09c287b 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H +#define NORTHBRIDGE_INTEL_E7505_E7505_H + /* * e7505.h: PCI configuration space for the Intel E7501 memory controller */ @@ -82,3 +85,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ diff --git a/src/northbridge/intel/e7520/e7520.h b/src/northbridge/intel/e7520/e7520.h index 61401e4..d3a71e6 100644 --- a/src/northbridge/intel/e7520/e7520.h +++ b/src/northbridge/intel/e7520/e7520.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_E7520_E7520_H +#define NORTHBRIDGE_INTEL_E7520_E7520_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* NORTHBRIDGE_INTEL_E7520_E7520_H */ diff --git a/src/northbridge/intel/e7525/e7525.h b/src/northbridge/intel/e7525/e7525.h index 61401e4..d7c3574 100644 --- a/src/northbridge/intel/e7525/e7525.h +++ b/src/northbridge/intel/e7525/e7525.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_E7525_E7525_H +#define NORTHBRIDGE_INTEL_E7525_E7525_H + #define IURBASE 0X14 #define MCHCFG0 0X50 #define MCHSCRB 0X52 @@ -37,3 +40,5 @@ #define DEVPRES1_D0F1 (1 << 5) #define DEVPRES1_D8F0 (1 << 1) #define MSCFG 0XF6 + +#endif /* NORTHBRIDGE_INTEL_E7525_E7525_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index bdf7e51..8a86279 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H +#define NORTHBRIDGE_INTEL_I82830_I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -49,3 +52,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 8786fd7..b09dea6 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_INTEL_I855_I855_H +#define NORTHBRIDGE_INTEL_I855_I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -74,3 +77,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* NORTHBRIDGE_INTEL_I855_I855_H */ diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h index 2df30a6..74cdaa6 100644 --- a/src/northbridge/via/cn400/cn400.h +++ b/src/northbridge/via/cn400/cn400.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_VIA_CN400_CN400_H +#define NORTHBRIDGE_VIA_CN400_CN400_H + #ifndef __PRE_RAM__ // HACK static inline void cn400_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn400_noop(device_t dev) #define RAM_COMMAND_MSR_LOW (const char) 0x03 #define RAM_COMMAND_CBR (const char) 0x04 #define RAM_COMMAND_MSR_HIGH (const char) 0x05 + +#endif /* NORTHBRIDGE_VIA_CN400_CN400_H */ diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h index ff1d4b3..f3f1d24 100644 --- a/src/northbridge/via/cn700/cn700.h +++ b/src/northbridge/via/cn700/cn700.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_VIA_CN700_CN700_H +#define NORTHBRIDGE_VIA_CN700_CN700_H + #if !defined (__PRE_RAM__) // HACK static inline void cn700_noop(device_t dev) @@ -54,3 +57,5 @@ static inline void cn700_noop(device_t dev) #define RAM_COMMAND_PRECHARGE 0x2 #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 + +#endif /* NORTHBRIDGE_VIA_CN700_CN700_H */ diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h index 67c3da4..730aa75 100644 --- a/src/northbridge/via/cx700/registers.h +++ b/src/northbridge/via/cx700/registers.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef NORTHBRIDGE_VIA_CX700_REGISTERS_H +#define NORTHBRIDGE_VIA_CX700_REGISTERS_H + /* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */ #define SCRATCH_REG_BASE 0xd0 #define SCRATCH_RANK_0 0xd0 @@ -42,3 +45,5 @@ #define DDRII_333 0x2 #define DDRII_266 0x1 #define DDRII_200 0x0 + +#endif /* NORTHBRIDGE_VIA_CX700_REGISTERS_H */ diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 00f8f50..50d3bfc 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -1,3 +1,6 @@ +#ifndef SOUTHBRIDGE_AMD_AMD8111_AMD8111_SMBUS_H +#define SOUTHBRIDGE_AMD_AMD8111_AMD8111_SMBUS_H + #include <device/smbus_def.h>
#define SMBGSTATUS 0xe0 @@ -323,3 +326,5 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne } return 0; } + +#endif /* SOUTHBRIDGE_AMD_AMD8111_AMD8111_SMBUS_H */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 1038f73..535c449 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_BD82X6X_NVS_H +#define SOUTHBRIDGE_INTEL_BD82X6X_NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -158,3 +161,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 8889f02..7e55b89 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_NVS_H +#define SOUTHBRIDGE_INTEL_FSP_BD82X6X_NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -156,3 +159,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_NVS_H */ diff --git a/src/southbridge/intel/fsp_rangeley/nvs.h b/src/southbridge/intel/fsp_rangeley/nvs.h index dce23e0..1cf483a 100644 --- a/src/southbridge/intel/fsp_rangeley/nvs.h +++ b/src/southbridge/intel/fsp_rangeley/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_FSP_RANGELEY_NVS_H +#define SOUTHBRIDGE_INTEL_FSP_RANGELEY_NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -153,3 +156,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* SOUTHBRIDGE_INTEL_FSP_RANGELEY_NVS_H */ diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 14f0ad3..9567d12 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_I82801DX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801DX_NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -135,3 +138,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +#endif /* SOUTHBRIDGE_INTEL_I82801DX_NVS_H */ diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 14f0ad3..1c68220 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_I82801GX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801GX_NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -135,3 +138,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 14f0ad3..8fa878a 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801IX_NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -135,3 +138,5 @@ typedef struct { u8 bten; u8 rsvd13[14]; } __attribute__((packed)) global_nvs_t; + +#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index b576cc1..f857c40 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,3 +1,6 @@ +#ifndef SOUTHBRIDGE_INTEL_I82870_82870_H +#define SOUTHBRIDGE_INTEL_I82870_82870_H + /* for io apic 1461 */ #define MBAR 0x10 #define ABAR 0x40 @@ -12,3 +15,5 @@ #define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero)
#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + +#endif /* SOUTHBRIDGE_INTEL_I82870_82870_H */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 1038f73..588be94 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H +#define SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -158,3 +161,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 48010ff..9d5ae72 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H +#define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H + #include "vendorcode/google/chromeos/gnvs.h" typedef struct { /* Miscellaneous */ @@ -134,3 +137,5 @@ typedef struct { /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); #endif + +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */ diff --git a/src/southbridge/nvidia/ck804/early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h index 9f89595..fb2be0b 100644 --- a/src/southbridge/nvidia/ck804/early_setup_ss.h +++ b/src/southbridge/nvidia/ck804/early_setup_ss.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_NVIDIA_CK804_EARLY_SETUP_SS_H +#define SOUTHBRIDGE_NVIDIA_CK804_EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* SOUTHBRIDGE_NVIDIA_CK804_EARLY_SETUP_SS_H */ diff --git a/src/southbridge/nvidia/ck804/early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h index cf25403..62dc1db 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.h +++ b/src/southbridge/nvidia/ck804/early_smbus.h @@ -1,5 +1,10 @@ +#ifndef SOUTHBRIDGE_NVIDIA_CK804_EARLY_SMBUS_H +#define SOUTHBRIDGE_NVIDIA_CK804_EARLY_SMBUS_H + int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); void enable_smbus(void); int smbus_read_byte(unsigned int, unsigned int); int smbus_write_byte(unsigned int, unsigned int, unsigned char); + +#endif /* SOUTHBRIDGE_NVIDIA_CK804_EARLY_SMBUS_H */ diff --git a/src/southbridge/nvidia/mcp55/early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h index 0aadc73..031ff72 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_ss.h +++ b/src/southbridge/nvidia/mcp55/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_NVIDIA_MCP55_EARLY_SETUP_SS_H +#define SOUTHBRIDGE_NVIDIA_MCP55_EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -219,3 +222,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* SOUTHBRIDGE_NVIDIA_MCP55_EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.h b/src/southbridge/ricoh/rl5c476/rl5c476.h index 71966a1..2720808 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.h +++ b/src/southbridge/ricoh/rl5c476/rl5c476.h @@ -18,12 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
- /* rl5c476 routines and defines*/ +#ifndef SOUTHBRIDGE_RICOH_RL5C476_RL5C476_H +#define SOUTHBRIDGE_RICOH_RL5C476_RL5C476_H
+ /* rl5c476 routines and defines*/
#include <stdint.h>
- /* the 16 bit control structure for ricoh cardbus bridge */ typedef struct pc16reg { u8 idrevs; @@ -92,3 +93,5 @@ typedef struct pc16reg { u8 resv9; u8 smpga0; } __attribute__ ((packed)) pc16reg_t; + +#endif /* SOUTHBRIDGE_RICOH_RL5C476_RL5C476_H */ diff --git a/src/southbridge/sis/sis966/early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h index b6aa7d7..d8226d5 100644 --- a/src/southbridge/sis/sis966/early_setup_ss.h +++ b/src/southbridge/sis/sis966/early_setup_ss.h @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_SIS_SIS966_EARLY_SETUP_SS_H +#define SOUTHBRIDGE_SIS_SIS966_EARLY_SETUP_SS_H + static const unsigned int pcie_ss_tbl[] = { 0x0C504103f, 0x0C504103f, @@ -218,3 +221,5 @@ static const unsigned int cpu_ss_tbl[] = { 0x0C5039037, 0x0C5039037, }; + +#endif /* SOUTHBRIDGE_SIS_SIS966_EARLY_SETUP_SS_H */ diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index f71fe17..58fe5e2 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_TI_PCI7420_PCI7420_H +#define SOUTHBRIDGE_TI_PCI7420_PCI7420_H + // 0844d060 (old) #define SYSCTL 0x80 // 08405061 #define RIMUX (1 << 0) @@ -47,3 +50,5 @@ #define INTB 1 #define INTC 2 #define INTD 3 + +#endif /* SOUTHBRIDGE_TI_PCI7420_PCI7420_H */ diff --git a/src/southbridge/via/common/via_early_smbus.h b/src/southbridge/via/common/via_early_smbus.h index aca920b..0f91548 100644 --- a/src/southbridge/via/common/via_early_smbus.h +++ b/src/southbridge/via/common/via_early_smbus.h @@ -17,6 +17,9 @@ * along with this program. If not, see http://www.gnu.org/licenses/. */
+#ifndef SOUTHBRIDGE_VIA_COMMON_VIA_EARLY_SMBUS_H +#define SOUTHBRIDGE_VIA_COMMON_VIA_EARLY_SMBUS_H + /** * @file via_early_sambus.h * @@ -54,3 +57,5 @@
#include <device/early_smbus.h> #include <arch/io.h> + +#endif /* SOUTHBRIDGE_VIA_COMMON_VIA_EARLY_SMBUS_H */ diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h index d2aab34..aee64c0 100644 --- a/src/southbridge/via/vt8237r/nvs.h +++ b/src/southbridge/via/vt8237r/nvs.h @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_VIA_VT8237R_NVS_H +#define SOUTHBRIDGE_VIA_VT8237R_NVS_H + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -43,3 +46,5 @@ typedef struct { u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ } __attribute__((packed)) global_nvs_t; + +#endif /* SOUTHBRIDGE_VIA_VT8237R_NVS_H */ diff --git a/src/southbridge/via/vt82c686/vt82c686.h b/src/southbridge/via/vt82c686/vt82c686.h index 7d2ac52..c2440d6 100644 --- a/src/southbridge/via/vt82c686/vt82c686.h +++ b/src/southbridge/via/vt82c686/vt82c686.h @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#ifndef SOUTHBRIDGE_VIA_VT82C686_VT82C686_H +#define SOUTHBRIDGE_VIA_VT82C686_VT82C686_H + /* Datasheets: * Name: VT82C686A "Super South" South Bridge * Link: http://www.datasheets.org.uk/datasheet.php?article=3510260 @@ -53,3 +56,5 @@ PCI_DEVICE_ID_VIA_82C686_4 0x3057 // Function 4, Power Management PCI_DEVICE_ID_VIA_82C686_5 0x3058 // Function 5, AC'97 Codec PCI_DEVICE_ID_VIA_82C686_6 0x3068 // Function 6, MC'97 Codec */ + +#endif /* SOUTHBRIDGE_VIA_VT82C686_VT82C686_H */
-
HAOUAS Elyes