[M] Change in coreboot[main]: soc/intel/soc: Remove save state handler code

[Arthur Heymans (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83068?usp=email )

Change subject: soc/intel/soc: Remove save state handler code
......................................................................

soc/intel/soc: Remove save state handler code

Change-Id: I08349fd4f8d0a3dcd64f70ddfc9d18abcafb9d3b
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/alderlake/smihandler.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smitraphandler.c
M src/soc/intel/elkhartlake/smihandler.c
M src/soc/intel/jasperlake/smihandler.c
M src/soc/intel/meteorlake/smihandler.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/tigerlake/smihandler.c
11 files changed, 31 insertions(+), 218 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/83068/1

diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c
index e1fc5a0..9909d36 100644
--- a/src/soc/intel/alderlake/smihandler.c
+++ b/src/soc/intel/alderlake/smihandler.c
@@ -14,7 +14,7 @@
    return 1;
 }

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index b8319f4..c60884b 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
 #include <gpio.h>
 #include <intelblocks/smihandler.h>
 #include <soc/iomap.h>
@@ -15,12 +14,7 @@
    return 1;
 }

-const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
-	return &em64t100_smm_ops;
-}
-
-const smi_handler_t southbridge_smi[32] = {
+const void (*southbridge_smi[32])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index ac25990..faebda0 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -20,7 +20,7 @@
    	heci1_disable();
 }

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 437c321..960db7a 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -10,120 +10,80 @@
 struct global_nvs;

/*
- * The register value is used with get_reg and set_reg
- */
-enum smm_reg {
-	RAX,
-	RBX,
-	RCX,
-	RDX,
-};
-
-struct smm_save_state_ops {
-	/* return io_misc_info from SMM Save State Area */
-	uint32_t (*get_io_misc_info)(void *state);
-
-	/* return value of the requested register from
-	 * SMM Save State Area
-	 */
-	uint64_t (*get_reg)(void *state, enum smm_reg reg);
-
-	void (*set_reg)(void *state, enum smm_reg reg, uint64_t val);
-};
-
-typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops);
-
-/*
- * SOC SMI Handler has to provide this structure which has methods to access
- * the SOC specific SMM Save State Area
- */
-const struct smm_save_state_ops *get_smm_save_state_ops(void);
-
-/*
  * southbridge_smi should be defined inside SOC specific code and should have
  * handlers for any SMI events that need to be handled. Default handlers
  * for some SMI events are provided in soc/intel/common/block/smm/smihandler.c
  */
-extern const smi_handler_t southbridge_smi[32];
+extern const void (*southbridge_smi[32])(void);

/*
  * This function should be implemented in SOC specific code to handle
  * the SMI event on SLP_EN. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_sleep(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_sleep(void);

/*
  * This function should be implemented in SOC specific code to handle
  * SMI_APM event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_apmc(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_apmc(void);

/*
  * This function should be implemented in SOC specific code to handle
  * SMI_PM1 event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_pm1(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_pm1(void);

/*
  * This function should be implemented in SOC specific code to handle
  * SMI_GPE0 event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_gpe0(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_gpe0(void);

/*
  * This function should be implemented in SOC specific code to handle
  * MC event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_mc(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_mc(void);

/*
  * This function should be implemented in SOC specific code to handle
  * minitor event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_monitor(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_monitor(void);
 /*
  * This function should be implemented in SOC specific code to handle
  * SMI_TCO event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_tco(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_tco(void);

/*
  * This function should be implemented in SOC specific code to handle
  * SMI PERIODIC_STS event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_periodic(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_periodic(void);

/*
  * This function should be implemented in SOC specific code to handle
  * SMI GPIO_STS event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_gpi(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_gpi(void);

/*
  * This function should be implemented in SOC specific code to handle
  * SMI ESPI_STS event. The default functionality is provided in
  * soc/intel/common/block/smm/smihandler.c
  */
-void smihandler_southbridge_espi(
-	const struct smm_save_state_ops *save_state_ops);
+void smihandler_southbridge_espi(void);

/* SoC overrides. */

@@ -143,8 +103,4 @@

/* Mainboard handler for ESPI EMIs */
 void mainboard_smi_espi_handler(void);
-
-extern const struct smm_save_state_ops em64t100_smm_ops;
-
-extern const struct smm_save_state_ops em64t101_smm_ops;
 #endif
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 27d9312..94082b6 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -6,9 +6,8 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
-#include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/msr.h>
+#include <cpu/x86/save_state.h>
 #include <delay.h>
 #include <device/mmio.h>
 #include <device/pci_def.h>
@@ -30,13 +29,6 @@
 #include <spi-generic.h>
 #include <stdint.h>

-/* SoC overrides. */
-
-__weak const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
-	return &em64t101_smm_ops;
-}
-
 /* Specific SOC SMI handler during ramstage finalize phase */
 __weak void smihandler_soc_at_finalize(void)
 {
@@ -116,8 +108,7 @@
    }
 }

-void smihandler_southbridge_sleep(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_sleep(void)
 {
    uint32_t reg32;
    uint8_t slp_typ;
@@ -277,8 +268,7 @@
    smihandler_soc_at_finalize();
 }

-void smihandler_southbridge_apmc(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_apmc(void)
 {
    uint8_t reg8;

@@ -306,8 +296,7 @@
    mainboard_smi_apmc(reg8);
 }

-void smihandler_southbridge_pm1(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_pm1(void)
 {
    uint16_t pm1_sts = pmc_clear_pm1_status();
    u16 pm1_en = pmc_read_pm1_enable();
@@ -324,14 +313,12 @@
    }
 }

-void smihandler_southbridge_gpe0(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_gpe0(void)
 {
    pmc_clear_all_gpe_status();
 }

-void smihandler_southbridge_tco(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_tco(void)
 {
    uint32_t tco_sts = pmc_clear_tco_status();

@@ -382,8 +369,7 @@
    }
 }

-void smihandler_southbridge_periodic(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_periodic(void)
 {
    uint32_t reg32;

@@ -398,8 +384,7 @@
    	oc_wdt_reload();
 }

-void smihandler_southbridge_gpi(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_gpi(void)
 {
    struct gpi_status smi_sts;

@@ -410,8 +395,7 @@
    gpi_clear_get_smi_status(&smi_sts);
 }

-void smihandler_southbridge_espi(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_espi(void)
 {
    mainboard_smi_espi_handler();
 }
@@ -420,7 +404,6 @@
 {
    int i;
    uint32_t smi_sts;
-	const struct smm_save_state_ops *save_state_ops;

/*
     * We need to clear the SMI status registers, or we won't see what's
@@ -441,15 +424,13 @@
    if (!smi_sts)
    	return;

-	save_state_ops = get_smm_save_state_ops();
-
    /* Call SMI sub handler for each of the status bits */
    for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
    	if (!(smi_sts & (1 << i)))
    		continue;

if (southbridge_smi[i] != NULL) {
-			southbridge_smi[i](save_state_ops);
+			southbridge_smi[i]();
    	} else {
    		printk(BIOS_DEBUG,
    		       "SMI_STS[%d] occurred, but no "
@@ -457,119 +438,3 @@
    	}
    }
 }
-
-static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state)
-{
-	em64t100_smm_state_save_area_t *smm_state = state;
-	return smm_state->io_misc_info;
-}
-
-static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg)
-{
-	uintptr_t value = 0;
-	em64t100_smm_state_save_area_t *smm_state = state;
-
-	switch (reg) {
-	case RAX:
-		value = smm_state->rax;
-		break;
-	case RBX:
-		value = smm_state->rbx;
-		break;
-	case RCX:
-		value = smm_state->rcx;
-		break;
-	case RDX:
-		value = smm_state->rdx;
-		break;
-	default:
-		break;
-	}
-	return value;
-}
-
-static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg,
-	uint64_t val)
-{
-	em64t100_smm_state_save_area_t *smm_state = state;
-	switch (reg) {
-	case RAX:
-		smm_state->rax = val;
-		break;
-	case RBX:
-		smm_state->rbx = val;
-		break;
-	case RCX:
-		smm_state->rcx = val;
-		break;
-	case RDX:
-		smm_state->rdx = val;
-		break;
-	default:
-		break;
-	}
-}
-
-static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state)
-{
-	em64t101_smm_state_save_area_t *smm_state = state;
-	return smm_state->io_misc_info;
-}
-
-static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg)
-{
-	uintptr_t value = 0;
-	em64t101_smm_state_save_area_t *smm_state = state;
-
-	switch (reg) {
-	case RAX:
-		value = smm_state->rax;
-		break;
-	case RBX:
-		value = smm_state->rbx;
-		break;
-	case RCX:
-		value = smm_state->rcx;
-		break;
-	case RDX:
-		value = smm_state->rdx;
-		break;
-	default:
-		break;
-	}
-	return value;
-}
-
-static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg,
-	uint64_t val)
-{
-	em64t101_smm_state_save_area_t *smm_state = state;
-	switch (reg) {
-	case RAX:
-		smm_state->rax = val;
-		break;
-	case RBX:
-		smm_state->rbx = val;
-		break;
-	case RCX:
-		smm_state->rcx = val;
-		break;
-	case RDX:
-		smm_state->rdx = val;
-		break;
-	default:
-		break;
-	}
-}
-
-const struct smm_save_state_ops em64t100_smm_ops = {
-	.get_io_misc_info = em64t100_smm_save_state_get_io_misc_info,
-	.get_reg = em64t100_smm_save_state_get_reg,
-	.set_reg = em64t100_smm_save_state_set_reg,
-};
-
-const struct smm_save_state_ops em64t101_smm_ops = {
-	.get_io_misc_info = em64t101_smm_save_state_get_io_misc_info,
-	.get_reg = em64t101_smm_save_state_get_reg,
-	.set_reg = em64t101_smm_save_state_set_reg,
-};
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c
index c7ef4e3..a5771ef 100644
--- a/src/soc/intel/common/block/smm/smitraphandler.c
+++ b/src/soc/intel/common/block/smm/smitraphandler.c
@@ -22,8 +22,7 @@
 #define PCR_PSTH_TRPD   0x1E18

-void smihandler_southbridge_mc(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_mc(void)
 {
    u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN);

@@ -34,8 +33,7 @@
    printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }

-void smihandler_southbridge_monitor(
-	const struct smm_save_state_ops *save_state_ops)
+void smihandler_southbridge_monitor(void)
 {
 #define IOTRAP(x) (trap_sts & (1 << x))
    u32 trap_cycle;
diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c
index eb5a576..d3b0f32 100644
--- a/src/soc/intel/elkhartlake/smihandler.c
+++ b/src/soc/intel/elkhartlake/smihandler.c
@@ -20,7 +20,7 @@
    	heci1_disable();
 }

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
index f2294fe..f21090e 100644
--- a/src/soc/intel/jasperlake/smihandler.c
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -28,7 +28,7 @@
    return 1;
 }

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/meteorlake/smihandler.c b/src/soc/intel/meteorlake/smihandler.c
index 6a21f0a..880a1b5 100644
--- a/src/soc/intel/meteorlake/smihandler.c
+++ b/src/soc/intel/meteorlake/smihandler.c
@@ -14,7 +14,7 @@
    return 1;
 }

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 177010c..5df890c 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -3,7 +3,7 @@
 #include <intelblocks/smihandler.h>
 #include <soc/pm.h>

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index e1fc5a0..9909d36 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -14,7 +14,7 @@
    return 1;
 }

-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const void (*southbridge_smi[SMI_STS_BITS])(void) = {
    [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,