[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)

[Alicja Michalska (Code Review)]

Attention is currently required from: Alicja Michalska, Felix Singer, Michał Żygowski, Nicholas Chin, Paul Menzel.

Hello Felix Singer, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/80853?usp=email

to look at the new patch set (#6).

The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)

Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
......................................................................

mb/erying: Add Erying Polestar G613 Pro (TGL-H)

Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.

Working:
- Serial port (IT8613E RS232)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports (somewhat)
- PCI-E Resizable BAR (ReBAR)
- VT-x (PCI-E passtrough, broken on stock)

WIP/Broken:
- PCI-E ASPM (even though I force-disabled it, I'm still getting AERs)
- M.2 NGFF WiFi (should be working, but I lost my WiFi card while
  moving)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
  system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (simple fix, need to re-configure GPIOs)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)

Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor haven't enabled any protections on SPI chip.

I'd like to get ASPM working as it makes big difference in idle power
consumtion (25 vs 60W measured from the wall at 230V).

Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot
the machine without `pcie_aspm=off` parameter:
- BadTLP
- BadDLLP
- Timeout
- Rollover

Adjusting LaneEq's didn't change anything, all settings are configured
in (mostly) the same way as they were on stock firmware.

Starting to suspect Intel's FSP might be buggy, as I haven't had those
issues when I initially started working on this project when 4.20 tree
was current.

TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.

Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska 
---
A src/mainboard/erying/Kconfig
A src/mainboard/erying/Kconfig.name
A src/mainboard/erying/tgl/Kconfig
A src/mainboard/erying/tgl/Kconfig.name
A src/mainboard/erying/tgl/Makefile.inc
A src/mainboard/erying/tgl/board_info.txt
A src/mainboard/erying/tgl/bootblock.c
A src/mainboard/erying/tgl/cmos.layout
A src/mainboard/erying/tgl/data.vbt
A src/mainboard/erying/tgl/devicetree.cb
A src/mainboard/erying/tgl/dsdt.asl
A src/mainboard/erying/tgl/gpio.h
A src/mainboard/erying/tgl/hda_verb.c
A src/mainboard/erying/tgl/ramstage.c
A src/mainboard/erying/tgl/romstage_fsp_params.c
15 files changed, 861 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/6