Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80641?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: mb/google/rex/var/rex0: Refactor SSD power sequencing ......................................................................
mb/google/rex/var/rex0: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy understanding:
bootblock (A20/0, A19/1) | v romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage.
TEST=Able to build and boot google/rex0 using NVMe without any problems. S0ix and read/write from/to SSD are also normal.
Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e Signed-off-by: Subrata Banik subratabanik@google.com --- M src/mainboard/google/rex/variants/rex0/gpio.c 1 file changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/80641/2