HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
mb/intel: Convert to ASL 2.0 syntax
Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 2 files changed, 75 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46081/1
diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index fa55794..ddb61b4 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -23,46 +23,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP & ((AVB0 & AVB1) & (AVB2 & AVB3))) { /* Marks the availability of all opregions */ - Store (1, AVP1) + AVP1 = 1 } Else { - Store (0, AVP1) + AVP1 = 0 } }
@@ -163,9 +162,9 @@ Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -197,9 +196,9 @@ Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -220,26 +219,26 @@ Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 2 */ - If (LLess (VSIC, 2)) { + If (VSIC < 2) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { VSIO = 3 } - Increment (VSIC) + VSIC++ } }
@@ -251,18 +250,18 @@ PowerResource (OVTH, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1)
- if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -270,7 +269,7 @@ Sleep(3)
VACT = 1 - if (LNotEqual (ACVA, 109)) { + if ACVA != 109) { /* Set ANA at 2.8152V */ ACVA = 109 } @@ -279,7 +278,7 @@ _SB.PCI0.I2C2.PMIC.CLKE()
VDCT = 1 - if (LNotEqual (DCVA, 12)) { + if (DCVA != 12) { /* Set CORE at 1.2V */ DCVA = 12 } @@ -293,8 +292,8 @@ }
Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { Sleep(2) _SB.PCI0.I2C2.PMIC.CLKD() Sleep(2) @@ -319,17 +318,17 @@ PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -338,7 +337,7 @@
/* Enable VCM regulator */ VCMC = 1 - if (LNotEqual (VCMV, 109)) { + if ((VCM !=, 109) { /* Set VCM value at 2.8152 V */ VCMV = 109 @@ -351,8 +350,8 @@ }
Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -522,46 +521,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP & ((AVB0 & AVB1) & (AVB2 & AVB3))) { /* Marks the availability of all opregions */ - Store (1, AVP2) + AVP2 = 1 } Else { - Store (0, AVP2) + AVP2 = 0 } }
@@ -669,9 +667,9 @@ Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -703,9 +701,9 @@ Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -726,13 +724,13 @@ Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { VSIO = 0 - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { VSIO = 3 } Release (MUTV) @@ -743,15 +741,15 @@ PowerResource (OVFI, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 0)) { + If (AVP2 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1)
VAX2 = 1 /* Enable VAUX2 */
- if (LNotEqual (AX2V, 52)) { + if (AX2V != 52) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 @@ -761,7 +759,7 @@ _SB.PCI0.I2C3.PMIC.CLKE()
VAX1 = 1 /* Enable VAUX1 */ - if (LNotEqual (AX1V, 19)) { + if (AX1V != 19) { /* Set VAUX1 as 1.2132V */ AX1V = 19 } @@ -778,8 +776,8 @@ }
Method (_OFF, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 1)) { + If (AVP2 == 1) { + If (STA == 1) { Sleep(2) _SB.PCI0.I2C3.PMIC.CLKD() Sleep(2) diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 0f83b05..6ff05f7 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -170,12 +170,12 @@ STXS(GPP_C15) Sleep(1) /* t2 */
- Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -187,7 +187,7 @@ /* Pull PWREN low */ CTXS(GPP_B23)
- Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -389,12 +389,12 @@ STXS(GPP_H12) Sleep(1) /* t2 */
- Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -410,7 +410,7 @@ CTXS(GPP_R6) #endif
- Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46081
to look at the new patch set (#3).
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
mb/intel: Convert to ASL 2.0 syntax
Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 2 files changed, 75 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46081/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46081
to look at the new patch set (#4).
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
mb/intel: Convert to ASL 2.0 syntax
Generated buils/dsdt.dsl for intel/kblrvp11 are same.
Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 2 files changed, 75 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46081/4
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46081
to look at the new patch set (#5).
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
mb/intel: Convert to ASL 2.0 syntax
Generated buils/dsdt.dsl for intel/kblrvp11 are same.
Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 2 files changed, 75 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46081/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/acpi/mipi_camera.asl:
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 31: One 1
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 79: Zero 0
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 117: Zero 0
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 129: One 1
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 154: Zero 0
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 157: (STA == Zero) STA == 0
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 372: (STA == Zero) STA == 0
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 508: One 1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
Patch Set 5:
Thx or the review. Angel, "One" and "Zero" are also a part a ASL+ syntax.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/acpi/mipi_camera.asl:
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 31: One
1
Sorry, not this one
"One" is in ASL 2.0
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 79: Zero
0
Sorry, "Zero" is in ASL 2.0 syntax
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 117: Zero
0
Done
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 129: One
1
Done
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 154: Zero
0
Done
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 157: (STA == Zero)
STA == 0
Ack
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 372: (STA == Zero)
STA == 0
Ack
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 508: One
1
Done
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46081
to look at the new patch set (#6).
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
mb/intel: Convert to ASL 2.0 syntax
Generated buils/dsdt.dsl for intel/kblrvp11 are same.
Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 2 files changed, 77 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46081/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
Patch Set 6: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/acpi/mipi_camera.asl:
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 31: One
Sorry, not this one […]
Done
https://review.coreboot.org/c/coreboot/+/46081/5/src/mainboard/intel/tglrvp/... PS5, Line 79: Zero
Sorry, "Zero" is in ASL 2. […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46081 )
Change subject: mb/intel: Convert to ASL 2.0 syntax ......................................................................
mb/intel: Convert to ASL 2.0 syntax
Generated buils/dsdt.dsl for intel/kblrvp11 are same.
Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/46081 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 2 files changed, 77 insertions(+), 79 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index fa55794..26108a2 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -23,46 +23,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVP1) + AVP1 = 1 } Else { - Store (0, AVP1) + AVP1 = 0 } }
@@ -163,9 +162,9 @@ Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -197,9 +196,9 @@ Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -220,26 +219,26 @@ Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 2 */ - If (LLess (VSIC, 2)) { + If (VSIC < 2) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { VSIO = 3 } - Increment (VSIC) + VSIC++ } }
@@ -251,18 +250,18 @@ PowerResource (OVTH, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1)
- if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -270,7 +269,7 @@ Sleep(3)
VACT = 1 - if (LNotEqual (ACVA, 109)) { + if (ACVA != 109) { /* Set ANA at 2.8152V */ ACVA = 109 } @@ -279,7 +278,7 @@ _SB.PCI0.I2C2.PMIC.CLKE()
VDCT = 1 - if (LNotEqual (DCVA, 12)) { + if (DCVA != 12) { /* Set CORE at 1.2V */ DCVA = 12 } @@ -293,8 +292,8 @@ }
Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { Sleep(2) _SB.PCI0.I2C2.PMIC.CLKD() Sleep(2) @@ -319,17 +318,17 @@ PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 0)) { + If (AVP1 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 @@ -338,7 +337,7 @@
/* Enable VCM regulator */ VCMC = 1 - if (LNotEqual (VCMV, 109)) { + if (VCMV != 109) { /* Set VCM value at 2.8152 V */ VCMV = 109 @@ -351,8 +350,8 @@ }
Method (_OFF, 0, Serialized) { - If (LEqual (AVP1, 1)) { - If (LEqual (STA, 1)) { + If (AVP1 == 1) { + If (STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -522,46 +521,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xB0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xB1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xB2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xB3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVP2) + AVP2 = 1 } Else { - Store (0, AVP2) + AVP2 = 0 } }
@@ -669,9 +667,9 @@ Method (CLKE, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -703,9 +701,9 @@ Method (CLKD, 0, Serialized) { /* save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) + Local0 = Acquire (MUTC, 1000) /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -726,13 +724,13 @@ Method (DOVD, 1, Serialized) { /* Save Acquire result so we can check for Mutex acquired */ - Store (Acquire (MUTV, 1000), Local0) + Local0 = Acquire (MUTV, 1000) /* Check for Mutex acquired */ - If (LEqual (Local0, Zero)) { + If (Local0 == 0) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { VSIO = 0 - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { VSIO = 3 } Release (MUTV) @@ -743,15 +741,15 @@ PowerResource (OVFI, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 0)) { + If (AVP2 == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1)
VAX2 = 1 /* Enable VAUX2 */
- if (LNotEqual (AX2V, 52)) { + if (AX2V != 52) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 @@ -761,7 +759,7 @@ _SB.PCI0.I2C3.PMIC.CLKE()
VAX1 = 1 /* Enable VAUX1 */ - if (LNotEqual (AX1V, 19)) { + if (AX1V != 19) { /* Set VAUX1 as 1.2132V */ AX1V = 19 } @@ -778,8 +776,8 @@ }
Method (_OFF, 0, Serialized) { - If (LEqual (AVP2, 1)) { - If (LEqual (STA, 1)) { + If (AVP2 == 1) { + If (STA == 1) { Sleep(2) _SB.PCI0.I2C3.PMIC.CLKD() Sleep(2) diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl index 0f83b05..ffecfd2 100644 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -154,7 +154,7 @@ Name (STA, Zero) Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(0,1) /* Clock 0, 19.2MHz */ @@ -170,12 +170,12 @@ STXS(GPP_C15) Sleep(1) /* t2 */
- Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -187,7 +187,7 @@ /* Pull PWREN low */ CTXS(GPP_B23)
- Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */ @@ -369,7 +369,7 @@ Name (STA, Zero) Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { - If ((STA == Zero)) + If (STA == 0) { /* Enable IMG_CLK */ MCON(1,1) /* Clock 1, 19.2MHz */ @@ -389,12 +389,12 @@ STXS(GPP_H12) Sleep(1) /* t2 */
- Store(1,STA) + STA = 1 } } Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { - If ((STA == One)) + If (STA == 1) { /* Disable IMG_CLK */ Sleep(1) /* t0+t1 */ @@ -410,7 +410,7 @@ CTXS(GPP_R6) #endif
- Store(0,STA) + STA = 0 } } Method (_STA, 0, NotSerialized) /* _STA: Status */
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)