John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
mb/google/volteer: Update settings for FPMCU on Halvor
Configure gpio settings for FPMCU on Halvor.
BUG=b:153680359 TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg.
Signed-off-by: John Su john_su@compal.corp-partner.google.com Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6 --- M src/mainboard/google/volteer/variants/halvor/gpio.c 1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44575/1
diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 85f956a..077a157 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -27,6 +27,8 @@ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* A18 : DDSP_HPDB ==> NC */ PAD_NC(GPP_A18, NONE), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), /* A23 : I2S1_SCLK ==> HP_INT_L */ @@ -48,6 +50,12 @@ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* C1 : SMBDATA ==> FPMCU_BOOT1 */ PAD_CFG_GPO(GPP_C1, 0, DEEP), @@ -59,6 +67,12 @@ PAD_NC(GPP_C11, NONE), /* C13 : UART1_TXD ==> NC */ PAD_NC(GPP_C13, NONE), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), @@ -143,6 +157,8 @@ PAD_NC(GPP_H16, NONE), /* H17 : DDPB_CTRLDATA ==> NC */ PAD_NC(GPP_H17, NONE), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H23 : IMGCLKOUT4 ==> NC */ PAD_NC(GPP_H23, NONE),
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
Patch Set 1: Code-Review+1
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
Patch Set 1: Code-Review+1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44575/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/halvor/gpio.c:
https://review.coreboot.org/c/coreboot/+/44575/1/src/mainboard/google/voltee... PS1, Line 160: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
Patch Set 1: Code-Review+1
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
Patch Set 1: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44575 )
Change subject: mb/google/volteer: Update settings for FPMCU on Halvor ......................................................................
mb/google/volteer: Update settings for FPMCU on Halvor
Configure gpio settings for FPMCU on Halvor.
BUG=b:153680359 TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg.
Signed-off-by: John Su john_su@compal.corp-partner.google.com Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44575 Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/halvor/gpio.c 1 file changed, 16 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved John Su: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 85f956a..077a157 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -27,6 +27,8 @@ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* A18 : DDSP_HPDB ==> NC */ PAD_NC(GPP_A18, NONE), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), /* A23 : I2S1_SCLK ==> HP_INT_L */ @@ -48,6 +50,12 @@ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* C1 : SMBDATA ==> FPMCU_BOOT1 */ PAD_CFG_GPO(GPP_C1, 0, DEEP), @@ -59,6 +67,12 @@ PAD_NC(GPP_C11, NONE), /* C13 : UART1_TXD ==> NC */ PAD_NC(GPP_C13, NONE), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), @@ -143,6 +157,8 @@ PAD_NC(GPP_H16, NONE), /* H17 : DDPB_CTRLDATA ==> NC */ PAD_NC(GPP_H17, NONE), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), /* H23 : IMGCLKOUT4 ==> NC */ PAD_NC(GPP_H23, NONE),