Change in coreboot[master]: arch/x86: smbios write 7 table using deterministic cache functions

[Subrata Banik (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/56121

to look at the new patch set (#2).

Change subject: arch/x86: smbios write 7 table using deterministic cache functions
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arch/x86: smbios write 7 table using deterministic cache functions

This patch makes use of deterministic cache helper functions, for
example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper
functions from arch/x86/cpu_common.c file.

Also, changed argument for get_number_of_caches() function that receives
cpu_get_max_cache_share() data directly.

TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output.
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0005, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE1
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 288 kB
        Maximum Size: 288 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Data
        Associativity: 12-way Set-associative

Handle 0x0006, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE1
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 192 kB
        Maximum Size: 192 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Instruction
        Associativity: 8-way Set-associative

Handle 0x0007, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE2
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 1280 kB
        Maximum Size: 1280 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unified
        Associativity: Unknown

Handle 0x0008, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE3
        Configuration: Enabled, Not Socketed, Level 3
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 12288 kB
        Maximum Size: 12288 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unified
        Associativity: 12-way Set-associative

Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3
Signed-off-by: Subrata Banik 
---
M src/arch/x86/smbios.c
1 file changed, 13 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/56121/2