Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh.
Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63625

to look at the new patch set (#3).

Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
......................................................................

soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status

This patch creates a helper function to clear HSFSTS_CTL (offset 0x04)
register Bits 0 to 4.

As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation,
it's important to clear all SPI outstanding status before setting SPI
lock bits.

BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4.

Signed-off-by: Subrata Banik 
Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63625/3