Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43199 )
Change subject: soc/intel/baytrail: Align with Braswell ......................................................................
soc/intel/baytrail: Align with Braswell
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/baytrail/smm.c 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43199/1
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index af85c82..3f3c53f 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> #include <arch/io.h> #include <device/mmio.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> +#include <device/device.h> +#include <device/pci.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/smm.h> @@ -60,9 +60,9 @@
/* Enable SMIs for the gpios that are set to trigger the SMI. */ for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) alt_gpio_reg |= (1 << i); - } + route_reg >>= 2; } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43199
to look at the new patch set (#3).
Change subject: soc/intel/baytrail/smm.c: Align with Braswell ......................................................................
soc/intel/baytrail/smm.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/baytrail/smm.c 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43199/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43199 )
Change subject: soc/intel/baytrail/smm.c: Align with Braswell ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43199 )
Change subject: soc/intel/baytrail/smm.c: Align with Braswell ......................................................................
soc/intel/baytrail/smm.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/smm.c 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index af85c82..3f3c53f 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> #include <arch/io.h> #include <device/mmio.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> +#include <device/device.h> +#include <device/pci.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/smm.h> @@ -60,9 +60,9 @@
/* Enable SMIs for the gpios that are set to trigger the SMI. */ for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) alt_gpio_reg |= (1 << i); - } + route_reg >>= 2; } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
-
Angel Pons (Code Review) -
Tim Wawrzynczak (Code Review)