Change in coreboot[master]: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0 - coreboot-gerrit

1 Jun 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55103 )
Change subject: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
......................................................................
Patch Set 1: Code-Review+2
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/55103
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Gerrit-Change-Number: 55103
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Reviewer: Raul Rangel rrangel@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Attention: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Attention: Felix Held felix-coreboot@felixheld.de
Gerrit-Comment-Date: Tue, 01 Jun 2021 15:19:59 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment