Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21175
Change subject: soc/intel/cannonlake: Init UPD params based on config ......................................................................
soc/intel/cannonlake: Init UPD params based on config
Initialize UPD params based upon config
Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/vr_config.c 6 files changed, 146 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21175/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 435ce2d..0c05057 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-y += vr_config.c
postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 62181a3..bee2517 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -20,6 +20,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <romstage_handoff.h> +#include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h>
@@ -68,6 +69,8 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; + const struct device *dev = SA_DEV_ROOT; + const config_t *config = dev->chip_info;
/* Set USB OC pin to 0 first */ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { @@ -79,6 +82,71 @@ }
mainboard_silicon_init_params(params); + + /* SATA */ + params->SataEnable = config->SataEnable; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + /* Lan */ + params->PchLanEnable = config->PchLanEnable; + + /* Audio */ + params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = + config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + params->XdciEnable = config->XdciEnable; + + /* eMMC and SD */ + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + params->ScsUfsEnabled = config->ScsUfsEnabled; + + params->Heci3Enabled = config->Heci3Enabled; + params->Device4Enable = config->Device4Enable; + params->SkipMpInit = config->FspSkipMpInit; + + /* VrConfig Settings for 5 domains + * 0 = System Agent, 1 = IA Core, 2 = Ring, + * 3 = GT unsliced, 4 = GT sliced */ + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); }
/* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ea9f7d7..48305fe 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -165,7 +165,7 @@ CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ } chipset_lockdown;
- uint8_t SkipMpInit; + uint8_t FspSkipMpInit; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 47f659a..2cd7dd9 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -66,4 +66,7 @@ NUM_VR_DOMAINS };
+void fill_vr_domain_config(void *params, + int domain, const struct vr_config *cfg); + #endif diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index ab0e19b..fdb13c5 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -15,12 +15,14 @@
#include <arch/io.h> #include <arch/early_variables.h> +#include <chip.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> #include <intelblocks/pmclib.h> #include <memory_info.h> +#include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <timestamp.h> @@ -63,8 +65,27 @@ run_postcar_phase(&pcf); }
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const config_t *config) +{ + int i; + uint32_t mask = 0; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + const struct device *dev = SA_DEV_ROOT; + const config_t *config = dev->chip_info; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); }
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c new file mode 100644 index 0000000..9db71b2 --- /dev/null +++ b/src/soc/intel/cannonlake/vr_config.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <fsp/api.h> +#include <soc/ramstage.h> +#include <soc/vr_config.h> + +static const struct vr_config default_configs[NUM_VR_DOMAINS] = { + +}; + +void fill_vr_domain_config(void *params, + int domain, const struct vr_config *chip_cfg) +{ + FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; + const struct vr_config *cfg; + + if (domain < 0 || domain >= NUM_VR_DOMAINS) + return; + + /* Use device tree override if requested. */ + if (chip_cfg->vr_config_enable) + cfg = chip_cfg; + else + cfg = &default_configs[domain]; + + vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; + vr_params->Psi1Threshold[domain] = cfg->psi1threshold; + vr_params->Psi2Threshold[domain] = cfg->psi2threshold; + vr_params->Psi3Threshold[domain] = cfg->psi3threshold; + vr_params->Psi3Enable[domain] = cfg->psi3enable; + vr_params->Psi4Enable[domain] = cfg->psi4enable; + vr_params->ImonSlope[domain] = cfg->imon_slope; + vr_params->ImonOffset[domain] = cfg->imon_offset; + vr_params->IccMax[domain] = cfg->icc_max; + vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; + vr_params->AcLoadline[domain] = cfg->ac_loadline; + vr_params->DcLoadline[domain] = cfg->dc_loadline; +}
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Pratikkumar V Prajapati (Code Review)