Change in coreboot[master]: soc/intel/alderlake: Set max Pkg C-states to Auto

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55706 )

Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto
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soc/intel/alderlake: Set max Pkg C-states to Auto

This patch configures max Pkg C-state to Auto which limits the max
C-state to deep C-state

Signed-off-by: V Sowmya 
Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 19 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 709ab3c..077a58d 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -71,6 +71,24 @@

#define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 |	\
    		    FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5)
+/*
+ * The Max Pkg Cstate
+ * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10,
+ * 254 - CPU Default , 255 - Auto.
+ */
+enum pkgcstate_limit {
+	LIMIT_C0_C1      = 0,
+	LIMIT_C2         = 1,
+	LIMIT_C3         = 2,
+	LIMIT_C6         = 3,
+	LIMIT_C7         = 4,
+	LIMIT_C7S        = 5,
+	LIMIT_C8         = 6,
+	LIMIT_C9         = 7,
+	LIMIT_C10        = 8,
+	LIMIT_CPUDEFAULT = 254,
+	LIMIT_AUTO       = 255,
+};

struct soc_intel_alderlake_config {

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 5b0d631..6faa393 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -533,6 +533,7 @@
    s_cfg->PsOnEnable = 1;
    /* Enable the energy efficient turbo mode */
    s_cfg->EnergyEfficientTurbo = 1;
+	s_cfg->PkgCStateLimit = LIMIT_AUTO;
 }

static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,