[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 - coreboot-gerrit

29 Jun 2023


      Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh.
Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email )
Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
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Patch Set 3:
(1 comment)
File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c:
https://review.coreboot.org/c/coreboot/+/76175/comment/9aec8df9_c974890e :
PS3, Line 43: (0x00 << 16), (0x5a << 16)
Nit: are the parens necessary there?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Gerrit-Change-Number: 76175
Gerrit-PatchSet: 3
Gerrit-Owner: Mario Scheithauer mario.scheithauer@siemens.com
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