[XS] Change in coreboot[main]: soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1
Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83861?usp=email )
Change subject: soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1 ......................................................................
soc/intel/cml, pci_ids: Fix IDs for Intel Comet Lake-S/H GT1
Acording to the Intel GPU list[1], these devices have the following IDs:
8086:9BA8 - Comet Lake-S GT1 [UHD Graphics 610] [2] 8086:9BA5 - Comet Lake-S GT1 [UHD Graphics 610]
8086:9BA4 - Comet Lake-H GT1 [UHD Graphics 610] [3] 8086:9BA2 - Comet Lake-H GT1 [UHD Graphics 610]
This can also be verified using devicehunt.com [2,3].
[1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20240731150632/https://devicehunt.com/ view/type/pci/vendor/8086/device/9BA8
[3] https://web.archive.org/web/20230928015210/https://devicehunt.com/ view/type/pci/vendor/8086/device/9BA4
Change-Id: I776f434f3627d6fbd046a92eb736b1ffcac8274a Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/include/device/pci_ids.h 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/83861/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 2a105bb..8ff52a6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4182,12 +4182,12 @@ #define PCI_DID_INTEL_CML_GT2_ULT_4 0x9B4C #define PCI_DID_INTEL_CML_GT1_ULX_1 0x9B20 #define PCI_DID_INTEL_CML_GT2_ULX_1 0x9B40 -#define PCI_DID_INTEL_CML_GT1_S_1 0x9B25 -#define PCI_DID_INTEL_CML_GT1_S_2 0x9B28 +#define PCI_DID_INTEL_CML_GT1_S_1 0x9BA5 +#define PCI_DID_INTEL_CML_GT1_S_2 0x9BA8 #define PCI_DID_INTEL_CML_GT2_S_1 0x9B45 #define PCI_DID_INTEL_CML_GT2_S_2 0x9B48 -#define PCI_DID_INTEL_CML_GT1_H_1 0x9B24 -#define PCI_DID_INTEL_CML_GT1_H_2 0x9B22 +#define PCI_DID_INTEL_CML_GT1_H_1 0x9BA4 +#define PCI_DID_INTEL_CML_GT1_H_2 0x9BA2 #define PCI_DID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DID_INTEL_CML_GT2_H_2 0x9B42 #define PCI_DID_INTEL_CML_GT2_S_G0 0x9BC8
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Maxim (Code Review)