[M] Change in coreboot[master]: Revert "Revert "mb/google/brya: Add romstage early graphics for brya""

[Jakub Czapiga (Code Review)]

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71705 )

Change subject: Revert "Revert "mb/google/brya: Add romstage early graphics for brya""
......................................................................

Revert "Revert "mb/google/brya: Add romstage early graphics for brya""

This reverts commit 43b7e60e3eba7787c3adc892e1ca902e1a918c2a.

Reason for revert: Reland commit 96d9b756690839c17b307a93b8a1898bd1c02ff5.

Signed-off-by: Jakub Czapiga 
Change-Id: I356af2b5289beed0a0f38d939f2df7242f65c345
---
M src/mainboard/google/brya/Makefile.inc
A src/mainboard/google/brya/gma-mainboard.ads
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
3 files changed, 59 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/71705/1

diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc
index c40f21c..ab80e32 100644
--- a/src/mainboard/google/brya/Makefile.inc
+++ b/src/mainboard/google/brya/Makefile.inc
@@ -4,6 +4,7 @@

romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += romstage.c
+romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads

ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/brya/gma-mainboard.ads b/src/mainboard/google/brya/gma-mainboard.ads
new file mode 100644
index 0000000..3b02f14
--- /dev/null
+++ b/src/mainboard/google/brya/gma-mainboard.ads
@@ -0,0 +1,13 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+   ports : constant Port_List :=
+     (eDP,
+      others => Disabled);
+end GMA.Mainboard;
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 70e7779..efc2fcb 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -123,7 +123,37 @@
    }"

device domain 0 on
-		device ref igpu on end
+		# The timing values can be derived from datasheet of display panel
+		# You can use EDID string to identify the type of display on the board
+		# use below command to get display info from EDID
+		# strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
+
+		# refer to display PRM document (Volume 2b: Command Reference: Registers)
+		# for more info on display control registers
+		# https://01.org/linuxgraphics/documentation/hardware-specification-prms
+		#+-----------------------------+---------------------------------------+-----+
+		#| Intel docs                  | devicetree.cb                         | eDP |
+		#+-----------------------------+---------------------------------------+-----+
+		#| Power up delay              | `gpu_panel_power_up_delay`            | T3  |
+		#+-----------------------------+---------------------------------------+-----+
+		#| Power on to backlight on    | `gpu_panel_power_backlight_on_delay`  | T7  |
+		#+-----------------------------+---------------------------------------+-----+
+		#| Power Down delay            | `gpu_panel_power_down_delay`          | T10 |
+		#+-----------------------------+---------------------------------------+-----+
+		#| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9  |
+		#+-----------------------------+---------------------------------------+-----+
+		#| Power Cycle Delay           | `gpu_panel_power_cycle_delay`         | T12 |
+		#+-----------------------------+---------------------------------------+-----+
+		device ref igpu on
+			register "panel_cfg" = "{
+			    .up_delay_ms = 200,
+			    .down_delay_ms = 50,
+			    .cycle_delay_ms = 500,
+			    .backlight_on_delay_ms = 1,
+			    .backlight_off_delay_ms = 200,
+			    .backlight_pwm_hz = 200,
+			}"
+		end
    	device ref dtt on end
    	device ref tbt_pcie_rp0 on end
    	device ref tbt_pcie_rp1 on end