Change in coreboot[master]: lippert/frontrunner-af: Fix PCI devices ASL

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59179 )

Change subject: lippert/frontrunner-af: Fix PCI devices ASL
......................................................................

lippert/frontrunner-af: Fix PCI devices ASL

There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.

There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.

Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
M src/mainboard/lippert/frontrunner-af/dsdt.asl
2 files changed, 11 insertions(+), 43 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
index 7472ffe..5968ff3 100644
--- a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
+++ b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
@@ -37,7 +37,6 @@

/*  GPIO0 or GEvent8 event  */
    	Method(_L18) {
-			Notify(_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
    		Notify(_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
    		Notify(_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
    		Notify(_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
index 70a9b2e..48d8375 100644
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl
@@ -41,8 +41,6 @@

#include "acpi/routing.asl"

-	#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
-
    /* Contains the supported sleep states for this chipset */
    #include <southbridge/amd/common/acpi/sleepstates.asl>

@@ -109,17 +107,7 @@
    			}
    		}  /* end AGPB */

-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(APS2) }   /* APIC mode */
-					Return (PS2)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* Dev3 is also an external GFX bridge, not used in Herring */
+			/* Dev 2 & 3 are external GFX bridges, not used in Family14 */

Device(PBR4) {
    			Name(_ADR, 0x00040000)
@@ -158,25 +146,6 @@
    			} /* end _PRT */
    		} /* end PBR7 */

-			/* GPP */
-			Device(PBR9) {
-				Name(_ADR, 0x00090000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(APS9) }   /* APIC mode */
-					Return (PS9)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR9 */
-
-			Device(PBRa) {
-				Name(_ADR, 0x000A0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PICM){ Return(APSA) }   /* APIC mode */
-					Return (PSA)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRa */
-
    		Device(PE20) {
    			Name(_ADR, 0x00150000)
    			Name(_PRW, Package() {0x18, 4})
@@ -210,17 +179,11 @@
    			} /* end _PRT */
    		} /* end PE23 */

-			/* PCI slot 1, 2, 3 */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			}

/* Describe the Southbridge devices */
+
+			#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
+
    		Device(STCR) {
    			Name(_ADR, 0x00110000)
    			#include "acpi/sata.asl"
@@ -351,8 +314,14 @@
    			#include "acpi/superio.asl"
    		} /* end LIBR */

-			Device(HPBR) {
+			/* PCI bridge */
+			Device(PIBR) {
    			Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
    		} /* end HostPciBr */

Device(ACAD) {