Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35666/1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 5fba04b..76184be 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -214,7 +214,6 @@ /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ @@ -250,6 +249,7 @@ /* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, UP_20K, NF1), /* SIO_PWRBTN# */ };
const struct pad_config *variant_gpio_table(size_t *num)
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35666
to look at the new patch set (#2).
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35666/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35666
to look at the new patch set (#3).
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35666/3
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35666
to look at the new patch set (#4).
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 section 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35666/4
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 4: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35666/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35666/4//COMMIT_MSG@15 PS4, Line 15: TEST=Hook up XDP on sarien platform, able to boot up into OS and stay Drallion platform
Hello Aamir Bohra, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35666
to look at the new patch set (#5).
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 section 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on drallion platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35666/5
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35666/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35666/4//COMMIT_MSG@15 PS4, Line 15: TEST=Hook up XDP on sarien platform, able to boot up into OS and stay
Drallion platform
Done
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 5: Code-Review+2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 6: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 6: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 section 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger.
BUG=N/A TEST=Hook up XDP on drallion platform, able to boot up into OS and stay at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik bora.guvendik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aamir Bohra aamir.bohra@intel.com Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Lijian Zhao lijian.zhao@intel.com --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index c7b0053..154fc5a 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -214,7 +214,6 @@ /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ @@ -250,6 +249,7 @@ /* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ };
const struct pad_config *variant_gpio_table(size_t *num)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35666/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35666/7//COMMIT_MSG@10 PS7, Line 10: EDS vol1 section 17-1. Can you please email me the doc# and version? I cannot find this recommendation in the EDS.
https://review.coreboot.org/c/coreboot/+/35666/7//COMMIT_MSG@11 PS7, Line 11: stay floating Is this because there is no PU on the board?
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35666 )
Change subject: mb/google/drallion: Adjust GPD3 pin termination ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35666/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35666/7//COMMIT_MSG@10 PS7, Line 10: EDS vol1 section 17-1.
Can you please email me the doc# and version? I cannot find this recommendation in the EDS.
Emailed it.
https://review.coreboot.org/c/coreboot/+/35666/7//COMMIT_MSG@11 PS7, Line 11: stay floating
Is this because there is no PU on the board?
Yes that's correct. When XDP is connected, it drives SIO_PWRBTN# signal low, causing power off.
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Aamir Bohra (Code Review) -
Bora Guvendik (Code Review)
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EricR Lai (Code Review)
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Furquan Shaikh (Code Review)
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Lijian Zhao (Code Review)
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Subrata Banik (Code Review)