Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST - coreboot-gerrit

3 Aug 2020


      Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 )
Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
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Patch Set 2:
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Patch Set 2: Code-Review+1
Actually, same as on ICL. CNL doesn't have `SkipMpInit`, it seems to be
somewhere between FSP 2.0 and 2.1.
Subrata, do you know what the lack of SkipMpInit for CNL implies?
SkipMpInit wasn't removed but moved from FSP-S to FSP-M. I checked the FSP binary. It does only set the lock if SkipMpInit=0.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912
Gerrit-Change-Number: 36356
Gerrit-PatchSet: 2
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