Patch set updated for coreboot: 1a8f632 AMD fam10: Refactor calls for HT configuration

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8558

-gerrit

commit 1a8f63209b9cd34fdc6958ceddcfc389d50a6ac2
Author: Kyösti Mälkki <[e-mail]>
Date:   Thu Mar 19 16:49:47 2015 +0200

    AMD fam10: Refactor calls for HT configuration
    
    Change-Id: Ic8fbafdfadbc4ef0896d93e61c8a54ce69297e07
    Signed-off-by: Kyösti Mälkki <[e-mail]>
---
 src/northbridge/amd/amdfam10/ht_config.c   | 71 +++++++++++++++++-------------
 src/northbridge/amd/amdfam10/ht_config.h   | 15 +++----
 src/northbridge/amd/amdfam10/northbridge.c | 33 +++++++-------
 3 files changed, 60 insertions(+), 59 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c
index 3110980..6eec534 100644
--- a/src/northbridge/amd/amdfam10/ht_config.c
+++ b/src/northbridge/amd/amdfam10/ht_config.c
@@ -47,54 +47,51 @@ struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 	return d;
 }
 
-
-void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
-				u32 busn_min, u32 busn_max, u32 segbit,
-				u32 nodes)
+void set_config_map_reg(struct bus *link)
 {
 	u32 tempreg;
 	u32 i;
+	u32 ht_c_index = get_ht_c_index(link);
+	u32 linkn = link->link_num & 0x0f;
+	u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff;
+	u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff;
+	u32 nodeid = amdfam10_nodeid(link->dev);
 
-	busn_min>>=segbit;
-	busn_max>>=segbit;
+	tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3;
+	tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8);
 
-	tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
-	for (i=0; i<nodes; i++) {
+	for (i=0; i < sysconf.nodes; i++) {
 		device_t dev = __f1_dev[i];
 		pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
 	}
 }
 
-void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
-					u32 busn_min, u32 busn_max, u32 nodes)
+void clear_config_map_reg(struct bus *link)
 {
 	u32 i;
+	u32 ht_c_index = get_ht_c_index(link);
 
-	for (i=0; i<nodes; i++) {
+	for (i=0; i < sysconf.nodes; i++) {
 		device_t dev = __f1_dev[i];
 		pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
 	}
 }
 
 
-u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
+static u32 ht_c_key(struct bus *link)
 {
-	u32 tempreg;
-	u32 ht_c_index = 0;
+	u32 nodeid = amdfam10_nodeid(link->dev);
+	u32 linkn = link->link_num & 0x0f;
+	u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3;
+	return val;
+}
 
-#if 0
-	tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8);
+static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo)
+{
+	u32 ht_c_index = 0;
 
-	for (ht_c_index=0;ht_c_index<4; ht_c_index++) {
-		reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4);
-		if (((reg & 0xffff) == 0x0000)) {  /*found free*/
-			break;
-		}
-	}
-#endif
-	tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
 	for (ht_c_index=0; ht_c_index<32; ht_c_index++) {
-		if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) {
+		if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) {
 			return ht_c_index;
 		}
 	}
@@ -108,14 +105,26 @@ u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
 	return	-1;
 }
 
-void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
-				u32 busn_min, u32 busn_max,
-				sys_info_conf_t *sysinfo)
+u32 get_ht_c_index(struct bus *link)
 {
-	u32 val;
-	val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8);
-	sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20);  // same node need segn are same
+	u32 val = ht_c_key(link);
+	return get_ht_c_index_by_key(val, &sysconf);
+}
+
+void store_ht_c_conf_bus(struct bus *link)
+{
+	u32 val = ht_c_key(link);
+	u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf);
+
+	u32 segn = (link->subordinate >> 8) & 0x0f;
+	u32 busn_min = link->secondary & 0xff;
+	u32 busn_max = link->subordinate & 0xff;
+
+	val |= (segn << 28) | (busn_max << 20) | (busn_min << 12);
 
+	sysconf.ht_c_conf_bus[ht_c_index] = val;
+	sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg;
+	sysconf.ht_c_num++;
 }
 
 u32 get_io_addr_index(u32 nodeid, u32 linkn)
diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h
index 08c5263..fcec368 100644
--- a/src/northbridge/amd/amdfam10/ht_config.h
+++ b/src/northbridge/amd/amdfam10/ht_config.h
@@ -20,6 +20,7 @@
 typedef struct amdfam10_sysconf_t sys_info_conf_t;
 
 /* FIXME */
+u32 amdfam10_nodeid(device_t dev);
 extern device_t __f1_dev[];
 
 struct dram_base_mask_t {
@@ -29,17 +30,11 @@ struct dram_base_mask_t {
 
 struct dram_base_mask_t get_dram_base_mask(u32 nodeid);
 
-void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
-				u32 busn_min, u32 busn_max, u32 segbit,
-				u32 nodes);
-void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
-					u32 busn_min, u32 busn_max, u32 nodes);
+u32 get_ht_c_index(struct bus *link);
+void store_ht_c_conf_bus(struct bus *link);
 
-void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
-				u32 busn_min, u32 busn_max,
-				sys_info_conf_t *sysinfo);
-
-u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo);
+void set_config_map_reg(struct bus *link);
+void clear_config_map_reg(struct bus *link);
 
 
 void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 8eee64c..c3f7856 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -114,7 +114,7 @@ static void f1_write_config32(unsigned reg, u32 value)
 	}
 }
 
-static u32 amdfam10_nodeid(device_t dev)
+u32 amdfam10_nodeid(device_t dev)
 {
 #if NODE_NUMS == 64
 	unsigned busn;
@@ -197,7 +197,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 
 		int i;
 		unsigned int next_unitid;
-		u32 ht_c_index;
 		u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
 		u32 max_devfn;
 
@@ -209,9 +208,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 		/* See if there is an available configuration space mapping
 		 * register in function 1.
 		 */
-		ht_c_index = get_ht_c_index(nodeid, link->link_num, &sysconf);
-
-		if(ht_c_index>=4) return max;
+		if (get_ht_c_index(link) >= 4)
+			return max;
 
 		/* Set up the primary, secondary and subordinate bus numbers.
 		 * We have no idea how many busses are behind this bridge yet,
@@ -239,8 +237,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 		ht_route_link(link, HT_ROUTE_SCAN);
 
 		/* set the config map space */
-
-		set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
+		set_config_map_reg(link);
 
 		/* Now we can scan all of the subordinate busses i.e. the
 		 * chain on the hypertranport link
@@ -265,20 +262,20 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 		/* We know the number of busses behind this bridge.  Set the
 		 * subordinate bus number to it's real value
 		 */
-		set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
-		sysconf.ht_c_num++;
+		if (0) {
+			/* Clear the extend reg. */
+			clear_config_map_reg(link);
+		}
 
-		{
-			// use ht_unitid_base to update hcdn_reg
-			u32 temp = 0;
-			for(i=0;i<4;i++) {
-				temp |= (ht_unitid_base[i] & 0xff) << (i*8);
-			}
+		set_config_map_reg(link);
 
-			sysconf.hcdn_reg[ht_c_index] = temp;
+		/* Use ht_unitid_base to update hcdn_reg. */
+		link->hcdn_reg = 0;
+		for (i = 0; i < 4;i++)
+			link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8);
+
+		store_ht_c_conf_bus(link);
 
-		}
-		store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf);
 		return link->subordinate;
 }