Change in coreboot[master]: mb/google/kahlee/variants/grunt: Enable BayHub720 driver

[Simon Glass (Code Review)]

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/25967

Change subject: mb/google/kahlee/variants/grunt: Enable BayHub720 driver
......................................................................

mb/google/kahlee/variants/grunt: Enable BayHub720 driver

Enable this driver along with power saving.

BUG=b:73726008
BRANCH=none
TEST=boot and see this message:
BayHub BH720: Power-saving enabled 110103
> From linux:

$ iotools pci_read32 2 0 0 0x90
0x00110103

Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c
Signed-off-by: Simon Glass 
---
M src/mainboard/google/kahlee/Kconfig
M src/mainboard/google/kahlee/variants/grunt/devicetree.cb
2 files changed, 8 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/25967/1

diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 22925f4..24881b5 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -36,6 +36,7 @@
    select SOC_AMD_PSP_SELECTABLE_SMU_FW
    select SOC_AMD_SMU_FANLESS
    select HAVE_ACPI_RESUME
+	select DRIVERS_GENERIC_BH720 if BOARD_GOOGLE_GRUNT

if BOARD_GOOGLE_BASEBOARD_KAHLEE

diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
index cfc3198..0d4ad09 100644
--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
@@ -58,11 +58,16 @@
    	device pci 0.0 on  end # Root Complex
    	device pci 1.0 on  end # Internal Graphics P2P bridge 0x98e4
    	device pci 1.1 on  end # Internal Multimedia
-		device pci 2.0 on  end # PCIe Host Bridge
+		device pci 2.0 on end # PCIe Host Bridge
    	device pci 2.1 on  end #
    	device pci 2.2 on  end #
    	device pci 2.3 on  end #
-		device pci 2.4 on  end #
+		device pci 2.4 on
+			chip drivers/generic/bayhub
+				register "power_saving" = "1"
+				device pci 00.0 on end
+			end
+		end #
    	device pci 2.5 on  end #
    	device pci 8.0 on  end # PSP
    	device pci 9.0 on  end # PCIe Host Bridge