Change in coreboot[master]: mb/google/brya/var/felwinter: Add Wifi SAR for felwinter

[Ian Feng (Code Review)]

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59718 )

Change subject: mb/google/brya/var/felwinter: Add Wifi SAR for felwinter
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mb/google/brya/var/felwinter: Add Wifi SAR for felwinter

Add wifi sar for felwinter.

BUG=b:206901900
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage.

Signed-off-by: Ian Feng 
Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/felwinter/variant.c
2 files changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59718/1

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 1f835d6..8b8942b 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -9,6 +9,10 @@
    	option MAX98360_ALC5682I_I2S	1
    	option MAX98360_ALC5682VS_I2S	2
    end
+	field TABLETMODE 12
+                option TABLETMODE_DISABLED	0
+                option TABLETMODE_ENABLED	1
+        end
 end

chip soc/intel/alderlake
diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c
index ee39ef0..5e1010b 100644
--- a/src/mainboard/google/brya/variants/felwinter/variant.c
+++ b/src/mainboard/google/brya/variants/felwinter/variant.c
@@ -3,6 +3,17 @@
 #include <chip.h>
 #include <fw_config.h>
 #include <baseboard/variants.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+	const char *filename = NULL;
+
+	if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED)))
+		filename = "wifi_sar_0.hex";
+
+	return filename;
+}

void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {