[XS] Change in coreboot[main]: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83680?usp=email )

Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox
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soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox

During the stages which use Cache-as-RAM (CAR), Coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. Hence update that config
for Brox. For other boards, since it is part of RO update it on need
basis.

BUG=None
TEST=Build Brox BIOS image and boot to OS.

Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83680/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 470dbf4..298572b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -191,12 +191,12 @@

config DCACHE_BSP_STACK_SIZE
    hex
+	default 0x88000 if BOARD_GOOGLE_BROX_COMMON
    default 0x80400
    help
      The amount of anticipated stack usage in CAR by bootblock and
      other stages. In the case of FSP_USES_CB_STACK default value will be
-	  sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
-	  (~1KiB).
+	  sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement.

config FSP_TEMP_RAM_SIZE
    hex